 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L Series TMP93CS44/S45 Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = (NMI , INT0), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (RUN and IDLE2 are not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP93CS44/S45 Low Voltage/Low Power CMOS 16-bit Microcontrollers TMP93CS44F/TMP93CS45F 1. Outline and Device Characteristics The TMP93CS44/TMP93CS45 are high-speed, advanced 16-bit microcontrollers developed for controlling medium to large-scale equipment. The TMP93CS45 does not have a ROM, the TMP93CS44 has a built-in ROM. Otherwise, the devices function in the same way. The TMP93CS44F/TMP93CS45F are housed in 80-pin flat package (P-LQFP80-1212-0.50E). The device characteristics are as follows: (1) Original 16-bit CPU (900/L CPU) * * * * * TLCS-90 instruction mnemonic upward compatible 16-Mbyte linear address space General-purpose registers and register bank system 16-bit multiplication/division and bit transfer/arithmetic instructions Micro DMA: 4 channels (1.6 s per 2 bytes at 20 MHz) (2) Minimum instruction execution time: 200 ns at 20 MHz (3) Internal RAM: 2 Kbytes Internal ROM: TMP93CS44 TMP93CS45 64-Kbyte ROM None (4) External memory expansion * * * Can be expanded up to 16 Mbytes (for both programs and data) AM8/ 16 pin (Select the external data bus width) Can mix 8- and 16-bit external data buses (Dynamic bus sizing) (5) 8-bit timer: 4 channels (6) 16-bit timer: 2 channels 030619EBP1 * The information contained herein is subject to change without notice. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 93CS44-1 2004-02-10 TMP93CS44/S45 (7) Serial interface: 2 channels (8) Serial bus interface: 1 channel * * I2C bus mode Clocked-synchronous 8-bit serial interface mode (9) 10-bit AD converter: 8 channels (10) High current output: 8 ports (11) Watchdog timer (12) Bus width/wait controller: 3 blocks (13) Interrupt functions: 33 * * * 9 CPU interrupts 17 internal interrupts 7 external interrupts 7-level priority can be set (except NMI and INTWD) (14) I/O ports TMP93CS44 TMP93CS45 62 pins 44 pins (15) Standby function: 4 HALT modes (RUN, IDLE2, IDLE1, STOP) (16) Clock gear function * * * Dual clock operation High-frequency clock can be changed from fc to fc/16 VCC = 2.7 to 5.5 V (17) Wide range of operating voltage (18) Package Type Number TMP93CS44F TMP93CS45F Package P-LQFP80-1212-0.50E 93CS44-2 2004-02-10 TMP93CS44/S45 AN0 to AN2 (P50 to P52) AN3/ ADTRG (P53) AN4 to AN7 (P54 to P57) AVCC AVSS VREFH VREFL 900/L CPU 10-bit 8-ch AD converter XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32-bits F SR PC Highfrequency OSC VCC [2] VSS [2] X1 X2 CLK Lowfrequency OSC XT1 (P66) XT2 (P67) AM8/ AM16 EA RESET TXD0 (P60) RXD0 (P61) SCLK0/ CTS0 (P62) TXD1 (P63) RXD1 (P64) SCLK1/ CTS1 (P65) Serial I/O (Channel 0) Serial I/O (Channel 1) ALE TEST1/TEST2 Interrupt controller INT0 (P35) NMI WAIT (P70) P71 P72 P73 P74 P75 P76 P77 INT1/TI0 (P40) Port 7 Watchdog timer 2-Kbyte RAM Port 0 AD0 to AD7* (P00 to P07) AD8 to AD15/A8 to A15* (P10 to P17) A0 to A7/A16 to A23* (P20 to P27) RD (P30) * WR (P31) * HWR /SCK (P32) 8-bit timer (Timer 0) 8-bit timer (Timer 1) Port 1 Port 2 8-bit timer (Timer 2) 8-bit timer (Timer 3) 64-Kbyte ROM INT4/TI4 (P42) INT5/TI5 (P43) TO4 (P44) INT6/TI6 (P45) INT7/TI7 (P46) TO6 (P47) 16-bit timer (Timer 4) 16-bit timer (Timer 5) Not included in the TMP93CS45 Port 3 TO3 (P41) Wait controller (3 blocks) Serial bus interface controller SO/SDA (P33) SI/SCL (P34) Note: The pin state after reset. Product TMP93CS44 AM8/ AM16 "H" level "H" level TMP93CS45 "L" level Pin Function after Reset Item in parentheses ( ) are the initial setting after reset. Except for "*" pins, item in parentheses ( ) are the initial setting after reset. Except for "*" pins, item in parentheses ( ) are the initial setting after reset. However, port 1 is initialized item of out parentheses. Figure 1.1 TMP93CS44/TMP93CS45 Block Diagram 93CS44-3 2004-02-10 TMP93CS44/S45 2. Pin Assignment and Functions The assignment of input and output pins for the TMP93CS44/TMP93CS45, their names and functions are described below. 2.1 Pin Assignment Figure 2.1.1 shows pin assignment of the TMP93CS44F/TMP93CS45F. P32 (HWR/SCK) P31(WR) P30 (RD) VCC P27 (A23/A7) P26 (A22/A6) P25 (A21/A5) P24 (A20/A4) P23 (A19/A3) P22 (A18/A2) P21 (A17/A1) P20 (A16/A0) P17 (AD15/A15) P16 (AD14/A14) P15 (AD13/A13) P14 (AD12/A12) P13 (AD11/A11) P12 (AD10/A10) P11 (AD9/A9) P10 (AD8/A8) 60 55 50 45 41 40 (SO/SDA) P33 (SI/SCL) P34 (INT0) P35 (TI0/INT1) P40 (TO3) P41 (TI4/INT4) P42 (TI5/INT5) P43 (TO4) P44 (TI6/INT6) P45 (TI7/INT7) P46 (TO6) P47 VREFH VREFL AVSS AVCC (AN0) P50 (AN1) P51 (AN2) P52 (AN3/ ADTRG ) P53 (AN4) P54 61 65 35 70 TMP93CS44F/45F QFP80 30 Top view 75 25 P07 (AD7) P06 (AD6) P05 (AD5) P04 (AD4) P03 (AD3) P02 (AD2) P01 (AD1) P00 (AD0) ALE VSS VCC TEST2 TEST1 P67 (XT2) P66 (XT1) RESET EA 80 10 15 20 1 5 21 X2 X1 AM8/ AM16 Figure 2.1.1 Pin Assignment (P-LQFP80-1212-0.50E) (TXD0) P60 (RXD0) P61 (SCLK0/CTS0) P62 (TXD1) P63 (RXD1) P64 (SCLK1/CTS1) P65 (WAIT) P70 P71 VSS P72 P73 P74 P75 P76 P77 CLK (AN5) P55 (AN6) P56 (AN7) P57 NMI 93CS44-4 2004-02-10 TMP93CS44/S45 2.2 Pin Names and Functions The names of input/output pins and their functions are described below. Table 2.2.1 to Table 2.2.3 show "Pin Names and Functions". Table 2.2.1 Pin Names and Functions (1/3) Pin Names P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30 RD Number of Pins 8 8 I/O Functions I/O Port 0: I/O port that allows selection of I/O on a bit basis 3 states Address/data (Lower): Bits 0 to 7 for address/data bus I/O Port 1: I/O port that allows selection of I/O on a bit basis 3 states Address/data (Upper): Bits 8 to 15 for address/data bus Output Address: Bits 8 to 15 for address bus 8 I/O Port 2: I/O port that allows selection of I/O on a bit basis (with pull-up resistor) Output Address: Bits 0 to 7 for address bus Output Address: Bits 16 to 23 for address bus 1 1 1 Output Port 30: Output port Output Read: Strobe signal for reading external memory Output Port 31: Output port Output Write: Strobe signal for writing data on pins AD0 to AD7 I/O Port 32: I/O port (with pull-up resistor) Output High write: Strobe signal for writing data on pins AD8 to AD15 I/O Mode clock SBI SIO mode clock 1 I/O Port 33: I/O port Output Serial send data I/O SBI I2C bus mode channel data 1 I/O Port 34: I/O port Input Serial receive data I/O SBI I2C bus mode clock 1 I/O Port 35: I/O port Input Interrupt request pin 0: Interrupt request pin with programmable level/rising edge 1 I/O Port 40: I/O port Input Timer input 0: Timer 0 input Input Interrupt request pin 1: Interrupt request pin with rising edge 1 1 I/O Port 41: I/O port Output Timer output 3: 8-bit timer 3 output I/O Port 42: I/O port Input Timer input 4: Timer 4 input Input Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge P31 WR P32 HWR SCK P33 SO SDA P34 SI SCL P35 INT0 P40 TI0 INT1 P41 TO3 P42 TI4 INT4 93CS44-5 2004-02-10 TMP93CS44/S45 Table 2.2.2 Pin Names and Functions (2/3) Number Pin Names of Pins P43 TI5 INT5 P44 TO4 P45 TI6 INT6 P46 TI7 INT7 P47 TO6 P50 to P52, P54 to P57 AN0 to AN2, AN4 to AN7 P53 AN3 ADTRG I/O I/O Port 43: I/O port Input Timer input 5: Timer 4 input Functions 1 Input Interrupt request pin 5: Interrupt request pin with rising edge 1 1 I/O Port 44: I/O port Output Timer output 4: Timer 4 output pin I/O Port 45: I/O port Input Timer input 6: Timer 5 input Input Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge 1 I/O Port 46: I/O port Input Timer input 7: Timer 5 input Input 1 7 Interrupt request pin 7: Interrupt request pin with rising edge I/O Port 47: I/O port Output Timer output 6: Timer 5 output pin Input Port 50 to Port 52, Port 54 to Port 57: Input port Input Analog input: Analog signal input for AD converter 1 Input Port53: Input port Input Analog input: Analog signal input for AD converter Input AD converter external start trigger input 1 1 1 I/O Port 60: I/O port (with pull-up resistor) Output Serial send data 0 I/O Port 61: I/O port (with pull-up resistor) Input Serial receive data 0 I/O Port 62: I/O port (with pull-up resistor) I/O Serial clock I/O 0 Input Serial data send enable 0 (Clear to send) 1 1 1 I/O Port 63: I/O port (with pull-up resistor) Output Serial send data 1 I/O Port 64: I/O port (with pull-up resistor) Input Serial receive data 1 I/O Port 65: I/O port (with pull-up resistor) I/O Serial clock I/O 1 Input Serial data send enable 1 (Clear to send) 1 1 I/O Port 66: I/O port (Open-drain output) Input Low-frequency oscillator connecting pin I/O Port 67: I/O port (Open-drain output) Output Low-frequency oscillator connecting pin P60 TXD0 P61 RXD0 P62 SCLK0 CTS0 P63 TXD1 P64 RXD1 P65 SCLK1 CTS1 P66 XT1 P67 XT2 93CS44-6 2004-02-10 TMP93CS44/S45 Table 2.2.3 Pin Names and Functions (3/3) Pin Names P70 WAIT Number of Pins 1 I/O Functions I/O Port 70: I/O port (High current output available) Input WAIT: Pin used to request CPU bus wait (It is active in (1 + N) WAIT mode. Set by the bus-width/wait control register) 7 1 1 1 1 1 1 1 1 1 1 I/O Port 71 to Port 77: I/O port (High current output available) Input Power supply pin for AD converter Input GND pin for AD converter (0 V) Input Pin for high-level reference voltage input to AD converter Input Pin for low-level reference voltage input to AD converter Input Non-maskable interrupt request pin: Interrupt request pin with falling edge. Can also be operated at falling and rising edges by program. Input High-frequency oscillator connecting pin Output High-frequency oscillator connecting pin Input Reset: Initializes TMP93CS44/S45. (with pull-up resistor) Output Address latch enable. Can be disabled for reducing noise. Output Clock output: Outputs "fSYS / 2" clock. Pulled-up during reset. Can be disabled for reducing noise. Input External access: "0" should be inputted with TMP93CS45. "1" should be inputted with TMP93CS44. Input Address mode: Selects external data bus width. (The case of TMP93CS44) "1" should be inputted. The data bus width for external access is set by chip select/WAIT control register, port 1 control register. (The case of TMP93CS45) "0" should be inputted with fixed 16-bit bus width or 16-bit bus interlarded with 8-bit bus. "1" should be inputted with fixed 8-bit bus width. Input Power supply pin (All VCC pins should be connected with GND (0 V).) Input GND pin (0 V) (All VSS pins should be connected with GND (0 V).) Output/Input TEST1 should be connected with TEST2 pin. Do not connect to any other pins. P71 to P77 AVCC AVSS VREFH VREFL NMI X1 X2 RESET ALE CLK EA 1 AM8/ AM16 1 VCC VSS TEST1/TEST2 2 2 2 Note: Built-in pull-up resistors can be released from the pins other than the RESET pin by software. 93CS44-7 2004-02-10 TMP93CS44/S45 3. Operation This section describes the functions and basic operational blocks of TMP93CS44/S45 devices. See the 7. "Points of Note and Restriction" for the using notice and restrictions for each block. 3.1 CPU TMP93CS44/S45 devices have a built-in high-performance 16-bit CPU (900/L CPU). (For CPU operation, see TLCS-900/L CPU in the previous section.) This section describes CPU functions unique to the TMP93CS44/S45 that are not described in the previous section. 3.1.1 Reset When resetting the TMP93CS44/S45 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then set the RESET input to low level at least for 10 system clocks (16 s at 20 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks. Clock gear is initialized 1/16 mode by reset operation. It means that the system clock mode fSYS is set to fc/32 (= fc/16 x 1/2). When reset is accepted, the CPU sets as follows: * Program counter (PC) according to reset vector that is stored FFFF00H to FFFF02H. PC<7:0> Stored data in location FFFF00H PC<15:8> Stored data in location FFFF01H PC<23:16> Stored data in location FFFF02H Stack pointer (XSP) for system mode to 100H. Bits IFF2 to IFF0 of status register to 111. (Sets mask register to interrupt level 7.) MAX bit of status register to 1. (Sets to maximum mode.) Bits RFP2 to RFP0 of status register to 000. (Sets register banks to 0.) * * * * When reset is released, instruction execution starts from PC (Reset vector). CPU internal registers other than the above are not changed. When reset is accepted, processing for built-in I/Os, ports, and other pins is as follows. * * * * Initializes built-in I/O registers as per specifications. Sets port pins (including pins also used as built-in I/Os) to general-purpose input/output port mode. Pulls up the CLK pin to "H" level. Sets the ALE pin to "L" level (the case of TMP93CS45), to High-impedance (High-Z) (the case of TMP93CS44). Note 1: By resetting, register in the CPU except program counter (PC), status register (SR) and stack pointer (XSP) and the data in internal RAM are not changed. Note 2: The CLK pin is pulled up to "H" level during reset. When the voltage is put down externally, there is possible to cause malfunctions. Figure 3.1.1 and Figure 3.1.2 show the reset timing chart of TMP93CS44 and TMP93CS45. 93CS44-8 2004-02-10 45 x 1 cycles omitted Total of 220 x 1 cycles omitted X1 CLK Sampling RESET Sampling A16 to A23 (P20 to P27 input mode) ALE Address Address Read RD AD0 to AD15 Figure 3.1.1 TMP93CS44 Reset Timing Chart 93CS44-9 Address Data output Address WR HWR (P32 input mode) (Input mode) (Input mode) AD0 to AD15 Write P20 to P27, P32, P60 to P65 P33 to P35, P40 to P47, P50 to P57, P70 to P77 P66, P67 (Output mode: Open-drain output) TMP93CS44/S45 2004-02-10 Internal pull up High-Z 45 x 1 cycles omitted Total of 220 x 1 cycles omitted X1 CLK Sampling RESET Sampling A16 to A23 (P20 to P27 input mode) ALE Address Address Address Data input Read RD AD0 to AD15 Figure 3.1.2 TMP93CS45 Reset Timing Chart Address Date output Address 93CS44-10 WR HWR (P32 input mode) (Input mode) (Input mode) AD0 to AD15 Write P20 to P27, P32, P60 to P65 P33 to P35, P40 to P47, P50 to P57, P70 to P77 P66, P67 (Output mode: Open-drain output) TMP93CS44/S45 2004-02-10 Internal pull up High-Z TMP93CS44/S45 3.1.2 AM8/ AM16 pin (1) TMP93CS44 Set this pin to "H". After reset, the CPU accesses the internal ROM with 16-bit bus width. The bus width when the CPU accesses an external area is set by bus width/wait control registers and the registers of port 1, which are described in section 3.6.3. (The value of this pin is ignored and the value set by register is active.) (2) TMP93CS45 1. With fixed 16-bit data bus external 16-bit data bus or 8-bit data bus is selectable Set this pm to "L". Port 1, AD8 to AD15 and A8 to A15 pins are fixed to AD8 to AD15 functions. The values set in port 1 control register and port 1 function register are invalid. The external data bus width is set by the bus width/wait control register which is described in section 3.6.3. It is necessary to set the program memory to be accessed to 16-bit data bus after reset. 2. With fixed external 8-bit data bus Set this pin to "H". Port l, AD8 to AD15 and A8 to A15 pins are fixed to A8 to A15 functions. The values set in port 1 control register and port 1 function register are invalid. The values of bit4 93CS44-11 2004-02-10 TMP93CS44/S45 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP93CS44/S45. 000000H 000080H 000100H Internal RAM (2 Kbytes) 000880H Internal I/O (128 bytes) 256-byte direct area (n) 64-Kbyte area (nn) External memory 010000H FF0000H 16-Mbyte area (r32) (-r32) (r32+) (r32 + d8/16) (r32 + r8/16) (nnn) 64-Kbyte internal ROM (TMP93CS44) External area for TMP93CS45 FFFF00H FFFFFFH Vector table (256 bytes) ( = Internal area) Figure 3.2.1 Memory Map 93CS44-12 2004-02-10 TMP93CS44/S45 3.3 Dual Clock, Standby Function Dual clock, standby control circuits consist of (1) System clock controller, (2) Prescaler clock controller and (3) Standby controller. The oscillator operating mode is classified to (a) Single clock mode (Only X1 and X2 pin), and (b) Dual clock mode (X1, X2, XT1 and XT2 pin). Figure 3.3.1 shows a transition figure. Figure 3.3.2 shows the block diagram. Figure 3.3.3 shows I/O registers. Table 3.3.1 shows the internal operation and system clock. Reset RUN mode (Stops only CPU) IDLE2 mode (Stops CPU and AD) Instruction Interrupt Instruction Interrupt Instruction Interrupt Release reset Instruction Interrupt NORMAL mode (fc/gear value/2) STOP mode (Stops all circuits) IDLE1 mode (Operates only osciIIator) (a) Single clock mode transition figure Reset RUN mode (Stops only CPU) IDLE2 mode (Stops CPU and AD) Release reset Instruction Interrupt Instruction Interrupt Instruction Interrupt Instruction Interrupt NORMAL mode (fc/gear value/2) Instruction IDLE1 mode (Operates only oscillator) RUN mode (Stops only CPU) IDLE2 mode (Stops CPU and AD) STOP mode (Stops all circuits) Instruction Interrupt Instruction Interrupt Instruction Interrupt SLOW mode (fs/2) Instruction IDLE1 mode (Operates only oscillator) (b) Dual clock mode transition figure Figure 3.3.1 Transition Figure The clock frequency input from X1, X2 pin is called fc and the clock frequency input from XT1, XT2 pin is called fs. The clock frequency selected by SYSCR1 93CS44-13 2004-02-10 TMP93CS44/S45 Table 3.3.1 Internal Operation and System Clock Oscillator Operating Mode High Frequency Low Frequency (fc) RESET NORMAL Single clock RUN IDLE2 IDLE1 STOP RESET NORMAL Dual clock SLOW RUN IDLE2 IDLE1 STOP Stop Oscillation Programmable Stop Programmable Oscillation Reset Operate Oscillation Stop Stop (fs) Reset Operate Reset Operate Stop only AD Stop Reset CPU Internal l/O System Clock fSYS fc/32 Programmable (fc/2, fc/4, fc/8, fc/16, fc/32) Stop fc/32 Programmable (fc/2, fc/4, fc/8, fc/16, fc/32) Operate fs/2 Programmable (fc/2, fc/4, fc/8, fc/16, fc/32, fs/2) Stop Oscillator being used as system clock: Oscillation Other oscillator: Programmable Stop Stop Stop only AD Stop 93CS44-14 2004-02-10 * Warm up (Changing clocks)... fc or fs * Warm up (Releasing STOP mode) ... fFPH * Watchdog timer... fSYS SYSCR0 fc fs Watchdog timer/ warm-up timer Run and stop TRUN Selector 8-bit timers 0, 1, 2 and 3 16-bit timers 4 and 5 Serial interfaces 0 and 1 9-bit prescaler Figure 3.3.2 Block Diagram of Dual Clock, Standby Circuits /4 Internal I/O ROM, RAM System clock fSYS CPU Lowfrequency oscillator 93CS44-15 fFPH SYSCR0 Selector SYSCR0 XT2 XT1 /2 /2 CLK WDMOD Selector fc/2 fc/4 fc/8 fc/16 Highfrequency oscillator SYSCR1 X2 fc /2 /4 /8 /16 TMP93CS44/S45 2004-02-10 X1 TMP93CS44/S45 System Clock Control Register 0 7 SYSCR0 (006EH) Bit symbol Read/Write After reset Function 1 Highfrequency oscillator (fc) 6 XTEN 0 Lowfrequency oscillator (fs) 5 RXEN 1 Highfrequency oscillator (fc) after released STOP mode 4 RXTEN 0 Lowfrequency oscillator (fs) after released STOP mode 3 RSYSCK R/W 0 2 WUEF 0 1 PRCK1 0 0 PRCK0 0 XEN Select clock Warm-up timer after released (Write) STOP mode 0: fc 1: fs 0: Don't care 1: Start timer (Read) 0: End warm up 1: Not end warm up Select prescaler clock 00: fFPH 01: fs 10: fc/16 11: (Reserved) 0: Stop 0: Stop 1: Oscillation 1: Oscillation 0: Stop 0: Stop 1: Oscillation 1: Oscillation System Clock Control Register 1 7 SYSCR1 (006FH) Bit symbol Read/Write After reset Function 0 Select system clock 0: fc 1: fs 6 5 4 3 SYSCK 2 GEAR2 R/W 1 1 GEAR1 0 0 GEAR0 0 Select gear value of high frequency (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) Clock Output Control Register 7 CKOCR (006DH) Bit symbol Read/Write After reset Function 0 Always write to "0". 6 - R/W 0 5 4 3 2 1 ALEEN R/W 0/1 (Note 2) ALE pin output control 0: High-Z output 1: ALE output 0 CLKEN 0/1 (Note 2) CLK pin output control 0: High-Z output 1: CLK output - Watchdog Timer Mode Control Register 7 WDMOD (005CH) Bit symbol Read/Write After reset Function 1 WDT control 6 WDTP1 0 WDT detection time 00: 2 /fSYS 01: 217/fSYS 19 10: 2 /fSYS 11: 221/fSYS 15 5 WDTP0 0 timer 4 WARM 0 Warm-up 0: 214/ frequency inputted 1: 216/ frequency inputted 3 HALTM1 R/W 0 HALT mode 00: RUN mode 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode 2 HALTM0 0 1 RESCR 0 0: Don't care 1: Connects WDT output to RESET pin internally. 0 DRVE 0 Pin state control in STOP mode 0: I/O off 1: Remains the state before halt WDTE 0: Disable 1: Enable Note 1: Note 2: Note 3: SYSCR1 Figure 3.3.3 I/O Registers about Dual Clock, Standby 93CS44-16 2004-02-10 TMP93CS44/S45 3.3.1 System Clock Controller The system clock controller generates system clock (fSYS) for CPU core and internal I/O. It contains two oscillation circuits and clock gear circuit for high frequency (fc). The register SYSCR1 High-frequency clock X1 X2 X1 X2 XT1 Low-frequency clock XT2 XT1 XT2 (Open) 74HCU04 Refer to chapter 5 "Application Circuit." (a) Crystal/ceramic resonator (b) External oscillator (c) Crystal resonator (d) External oscillator Figure 3.3.4 Examples of Resonator Connection Note 1: Note on using the low-frequency oscillation circuit. In connecting the low-frequency resonator to ports 66 and 67, it is necessary to make the following settings to reduce the power consumption. (Connecting with resonators) P6CR 93CS44-17 2004-02-10 TMP93CS44/S45 (1) Switching from NORMAL to SLOW mode When the resonator is connected to X1, X2, or XT1, XT2 pin, the warm-up timer is used to change the operation frequency after getting stabilized oscillation. The warm-up time can be selected by WDMOD 0 (214/frequency) 1 (216/frequency) Change to NORMAL 0.8192 (ms) 3.2768 (ms) Change to SLOW 500 (ms) 2000 (ms) at fc = 20 MHz, fs = 32.768 kHz 93CS44-18 2004-02-10 TMP93CS44/S45 Clock setting example 1: Changing from the high frequency (fc) to the low frequency (fs). SYSCR0 SYSCR1 WDCR WDMOD EQU EQU EQU EQU RES LD SET SET SET BIT JR SET RES SET 006EH 006FH 005DH 005CH 7, (WDMOD) (WDCR), B1H 4, (WDMOD) 6, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) 7, (SYSCR0) 7, (WDMOD) WUP: ; ; ; ; ; ; ; ; ; ; Disables watchdog timer. Sets warm-up time to 216/fs. Enables low-frequency oscillation Clears and starts warm-up timer. Detects end of warm-up timer. Changes fSYS from fc to fs. Disables high-frequency oscillation. Enables watchdog timer. Enables low frequency Clears and starts warm-up timer Changes fSYS Disables from fc to fs high frequency End of warm-up timer fc fs Counts up by fSYS Counts up by fs 93CS44-19 2004-02-10 TMP93CS44/S45 Clock setting example 2: Changing from the low frequency (fs) to the high frequency (fc). SYSCR0 SYSCR1 WDCR WDMOD EQU EQU EQU EQU RES LD SET SET SET BIT JR SET RES SET 006EH 006FH 005DH 005CH 7, (WDMOD) (WDCR), B1H 4, (WDMOD) 7, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) 6, (SYSCR0) 7, (WDMOD) WUP: ; ; ; ; ; ; ; ; ; ; Disables watchdog timer. Sets warm-up time to 214/fc. Enables high-frequency (fc). Clears and starts warm-up timer. Detects end of warm-up timer. Changes fSYS from fs to fc. Disables low-frequency oscillation. Enable watchdog timer. Enables high frequency Clears and starts warm-up timer Change fSYS from fs to fc End of warm-up timer Disables low frequency fs fc Counts up by fSYS Counts up by fc 93CS44-20 2004-02-10 TMP93CS44/S45 (2) Clock gear controller When the high-frequency clock fc is selected at SYSCR1 SYSCR1 EQU 006FH LD LD X: Don't care (SYSCR1), XXXX0000B (SYSCR1), XXXX0100B ; Changes fSYS to fc/2. ; Changes fSYS to fc/32. (High-frequency clock gear changing) To change the frequency of the clock gear, write the value to SYSCR1 Example: SYSCR1 EQU LD LD 006FH (SYSCR1), XXXX0001B (DUMMY), 00H ; Changes fSYS to fc/4. ; Dummy instruction. Instruction to be executed by the clock gear after changing X: Don't care 93CS44-21 2004-02-10 TMP93CS44/S45 3.3.2 Prescaler Clock Controller The 9-bit prescaler provides a clock to 8-bit timer 0, 1, 2, 3, 16-bit timer 4, 5, and serial interface 0, 1. The clock input to the 9-bit prescaler is selected either fFPH, fc/16, or fs by SYSCR0 3.3.3 Internal Clock Pin Output Function CLK pin outputs fSYS divided by 2 internal clock. Outputs are specified by the clock output control register CKOCR TMP93CS44 TMP93CS45 CKOCR 0 1 CLK Pin Operation High impedance fSYS/2 clock output Note: To set 93CS44-22 2004-02-10 TMP93CS44/S45 3.3.4 Standby Controller (1) HALT mode When the HALT instruction is executed, the operating mode changes RUN, IDLE2, IDLE1 or STOP mode depending on the contents of the HALT mode setting register WDMOD WDMOD (005CH) Bit symbol Read/Write After reset Function 1 Watchdog timer control 0: Disable 1: Enable 6 WDTP1 0 5 WDTP0 0 timer 4 WARM 0 Warm-up 0: 2 /clock frequency selection 1: 2 /clock frequency selection 16 14 3 HALTM1 R/W 0 2 HALTM0 0 1 RESCR 0 Runaway detection internal reset control 1: Executes internal reset by runaway detection 0 DRVE 0 STOP mode pin control 1: Drive pins in STOP mode WDTE Watchdog timer detect time selection HALT mode selection 00: 01: 10: 11: RUN mode STOP mode IDLE1 mode IDLE2 mode 00: 215/fSYS 01: 217/fSYS 10: 219/fSYS 11: 221/fSYS Pin state control in STOP mode 0 I/O off 1 Retains the state before halt HALT mode setting 00 RUN mode (Only CPU stop) 01 10 11 STOP mode (All circuits stop) IDLE1 mode (Only oscillator operating) IDLE2 mode (Partial I/O operating) Warm-up time selection at returning from the stop mode (see Table 3.3.6) 0 214/select clock frequency 1 216/select clock frequency Figure 3.3.5 Watchdog Timer Mode Register The futures of RUN, IDLE2, IDLE1 and STOP modes are as follows. 1. RUN: Only the CPU halts; power consumption remains unchanged. 2. IDLE2: The built-in oscillator and the specified I/O operates. The power consumption is reduced to 1/2 than that during NORMAL operation. 3. IDLE1: Only the built-in oscillator operates, while all other built-in circuits stop. Consumption is reduced to 1/5 or less than that during NORMAL operation. 4. STOP: All internal circuits including the built-in oscillator stop. This greatly reduces power consumption. 93CS44-23 2004-02-10 TMP93CS44/S45 The operations in the halt state is described in Table 3.3.4. Table 3.3.4 I/O Operation during HALT Mode HALT mode WDMOD Keep the state when the "HALT" instruction was executed. See Table 3.3.7 IDLE1 10 STOP 01 (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combinations between the states of interrupt mask register * 93CS44-24 2004-02-10 TMP93CS44/S45 Table 3.3.5 Halt Releasing Source and Halt Releasing Operation Interrupt Receiving Status HALT mode NMI INTWDT INT0 INT1, INT4 to INT7 Halt releasing Interrupt source Interrupt Enable (Interrupt level) (Interrupt mask) Interrupt Disable (Interrupt level) < (Interrupt mask) INTT0 to INTT3 INTTR4 to INTTR7 INTTO4, INTTO5 INTRX0, INTTX0 INTRX1, INTTX1 INTS2 INTAD RESET RUN IDLE2 x IDLE1 x STOP *1 x RUN - - IDLE2 - - IDLE1 - - STOP - - x x x x x x x x x *1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x *1 x x x x x x x x : : x: -: After releasing the HALT mode, CPU starts interrupt processing. (RESET initializes LSI.) After releasing the HALT mode, CPU starts executing an instruction that follows the HALT instruction. It can not be used to release the HALT mode. This combination type does not exist because the priority level (Interrupt request level) of non-maskable interrupts is fixed to highest priority level "7". Releasing the HALT mode is executed after passing the warm-up time. When releasing the HALT mode is executed by INT0 interrupt of the level mode in the interrupt enabled status, hold level "H" until starting interrupt processing. If level "L" is set before holding level "L", interrupt processing is correctly started. *1: Note: (Example releasing "RUN" mode) INT0 interrupt releases halt state when the RUN mode is on. Address 8203H 8206H 8209H 820BH 820EH INT0 820FH LD XX, XX LD LD EI LD HALT (IIMC), 00H (INTE0AD), 06H 5 (WDMOD), 00H ; Selects interrupt rising edge for INT0. ; Sets interrupt level to "6" for INT0. ; Sets interrupt level to "5" for CPU. ; Sets HALT mode to "RUN". ; Halts CPU. INT0 interrupt routine RETI When halt is released by reset, the states (Including those of the internal RAM) before halt state was entered can be maintained. However, if the HALT instruction is executed within the internal RAM, the contents of the RAM may not be maintained. In this case, we recommend releasing the halt state using INT0. 93CS44-25 2004-02-10 TMP93CS44/S45 (3) Operation 1. RUN mode In the RUN mode, the system clock continues to operate even after a HALT instruction is executed. Only the CPU stops executing the instruction. In the halt state, an interrupt request is sampled with the falling edge of the "CLK" signal. Releasing the RUN mode is executed by the external/internal interrupts. (See Table 3.3.5 "Halt Releasing Source and Halt Releasing Operation".) Figure 3.3.6 shows the interrupt timing for releasing the halt state by interrupts in the RUN/IDLE2 mode. X1 CLK A0 to A23 ALE AD0 to AD15 RD WR NMI Address Data Address Address Data Address Address + 2 INT0 (Level) INT1, INT4 to INT7 (Rising edge) INT4, INT6 (Falling edge) Internal INT RUN/IDLE2 mode Figure 3.3.6 Timing Chart for Releasing the Halt State by Interrupt in RUN/IDLE2 Modes 2. IDLE2 mode In the IDLE2 mode, the system clock is supplied to only specific internal I/O devices, and the CPU stops executing the current instruction. In the IDLE2 mode, the halt state is released by an interrupt with the same timing as in the RUN mode. The IDLE2 mode is released by external/internal interrupt, except INTWDT/INTAD interrupts. (See Table 3.3.5 "Halt Releasing Source and Halt Releasing Operation".) In the IDLE2 mode, the watchdog timer should be disabled before entering the halt status to prevent the watchdog timer interrupt occurring just after releasing the HALT mode. 93CS44-26 2004-02-10 TMP93CS44/S45 3. IDLE1 mode In the IDLE1 mode, only the internal oscillator operates. The system clock in the MCU stops, the CLK pin is fixed at the level "H" in the output enable (CKOCR X1 CLK A0 to A23 ALE AD0 to AD15 RD WR NMI Address Data Address Data Address Address + 2 INT0 (Level) INT0 (Rising edge) IDLE1 mode Figure 3.3.7 Timing Chart of Halt Released by Interrupts in IDLE1 Mode 93CS44-27 2004-02-10 TMP93CS44/S45 4. STOP mode The STOP mode is selected to stop all internal circuits including the internal oscillator. The pin status in the STOP mode depends on setting of a bit in the watchdog timer mode register WDMOD Warm-up time X1 CLK A0 to A23 ALE AD0 to AD15 RD WR NMI Address Data Address Data Address Address + 2 INT0 (Level) INT0 (Rising edge) STOP mode Figure 3.3.8 Timing Chart of Halt State Release by Interrupts in STOP Mode 93CS44-28 2004-02-10 TMP93CS44/S45 Table 3.3.6 The Example of Warm-up Time after Releasing the STOP Mode Warm-up Time [ms] Clock Operation Frequency after the STOP Mode WDMOD fc fc/2 fc/4 fc/8 fc/16 fs 0.8192 1.6384 3.2768 6.5536 13.1072 500 3.2768 6.5536 13.1072 26.2144 52.4288 2000 fs = 32.768 kHz fc = 20 MHz Clock Frequency How to calculate the warm-up time 14 WDMOD Address SYSCR0 SYSCR1 WDMOD 8FFDH 9000H 9002H 9005H NMI EQU EQU EQU LD RES LD HALT 006EH 006FH 005CH (SYSCR1), 08H 4, (WDMOD) (SYSCR0), -11000 - - B ; fSYS = fs/2. ; Sets warm-up time to 214/fc. ; Operates high frequency after released. Clears and starts warm-up timer. (High frequency) End NMI Interrupt routine. 9006H LD XX, XX RETI -: No change Note: When different modes are used before and after STOP mode as the above mentioned, there is possible to release the HALT mode without changing the operation mode by acceptance of the halt release interrupt request during execution of "HALT" instruction (during 8 states). In the system which accepts the interrupts during execution "HALT" instruction, set the same operation mode before and after the STOP mode. 93CS44-29 2004-02-10 TMP93CS44/S45 Table 3.3.7 Pin States in STOP Mode Pin Name P00 to P07 Input mode Output mode AD0 to AD7 P10 to P17 Input mode Output mode/A8 to A15 AD8 to AD15 P20 to P27 Input mode Output mode A0 to A7/A16 to A23 P30 (RD), P31 (WR) P32 (HWR/SCK) P33 to P35 P40 to P47 P50 to P57 P60 to P65 P70 to P77 NMI I/O TMP93CS44 High-Z High-Z High-Z High-Z High-Z PU* PU* Invalid High-Z Invalid High-Z PU* PU* Invalid High-Z Input "L" level output High-Z Input "H" level fix "H" level fix Invalid "H" level output Invalid High-Z Invalid High-Z TMP93CS45 x x High-Z x x High-Z High-Z Output High-Z Output High-Z Output Output PU Output Invalid Output Invalid Output PU Output Invalid Output Input "L" level output "H" level output Input "H" level fix "H" level fix Invalid "H" level output Invalid Output* Invalid Output* x x High-Z x x High-Z Output "H" level output Output Input mode Output mode Input mode Output mode Input mode Output mode Input Input mode Output mode Input mode Output mode Input Output ( The same as for TMP93CS44 ALE CLK RESET EA "L" level fix Input "L" level fix Input AM8/ AM16 X1 X2 P66 The same as for TMP93CS44 P67 Input mode Output mode XT2 Input: Input gate in operation. Fix input voltage to 0 or 1 so that the input pin stays constant. Output: Output state. Output*: Open-drain output state. Input gate in operation. Set output to "L" or attach pull up on pin so that the input gate stays constant. Invalid: Input is not accepted. High-Z: Output is at high impedance. PU: Programmable pull-up pin in input gate in operation. Fix the pin to avoid through current since the input gate operates when a pull-up pin resistor is not set. PU*: Programmable pull-up pin in input gate disable state. No through current even if the pin is set to high impedance. : When a HALT instruction is executed and the CPU stops at the address of the port register, an input gate operates. Fix the pin to avoid through current, and change the program. Cannot set. x: : To connect a low-frequency resonator to port 66 and port 67, it is necessary to set the following procedures to reduce the consumption power supply. (Connecting to a resonater) Set P6CR 93CS44-30 2004-02-10 TMP93CS44/S45 3.4 Interrupts TLCS-900 interrupts are controlled by the CPU interrupt mask flip-flop External interrupts ........................... 7 A fixed individual interrupt vector number is assigned to each interrupt source; six levels of priority can also be assigned to each maskable interrupt. Non-maskable interrupts have a fixed priority of 7. When an interrupt is generated, the interrupt controller sends the value of the priority of the interupt source to the CPU. When more than one interrupt is generated simultaneously, the interrupt controller sends the value of the highest priority (7 for non-maskable interrupts is the highest) to the CPU. The CPU compares the value of the priority sent with the value in the CPU interrupt mask register 93CS44-31 2004-02-10 TMP93CS44/S45 Interrupt processing Read interrupt vector V. Clear interrupt request F/F. Start vector match of vector V and micro DMA No PUSH PC PUSH SR SR Yes Data transfer by micro DMA General-purpose interrupt processing COUNT COUNT - 1 Micro DMA processing Yes PC (FFFF00H + V) COUNT = 0 No Interrupt processing program RETI instruction POP SR POP PC INTNEST INTNEST - 1 End Figure 3.4.1 Interrupt Processing Flowchart 93CS44-32 2004-02-10 TMP93CS44/S45 3.4.1 General-purpose Interrupt Processing When accepting an interrupt, the CPU operates as follows. In the cases of software interrupts or interrupts generated by the CPU because of attempts to execute illegal instructions, the following steps (1) and (3) are not executed. (1) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same level is generated simultaneously, the interrupt controller generates interrupt vectors in accordance with the default priority (which is fixed as follows: The smaller the vector value, the higher the priority), then clears the interrupt request. (2) The CPU pushes the program counter and the status register to the system stack area (Area indicated by the system mode stack pointer (XSP)). (3) The CPU sets a value in the CPU interrupt mask register 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits Interrupt Processing State Number 35 31 29 25 To return to the main routine after completion of the interrupt processing, the RETI instruction is usually used. Executing this instruction restores the contents of the program counter and the status registers and decrements INTNEST (Interrupt nesting counter). Though acceptance of non-maskable interrupts cannot be disabled by program, acceptance of maskable interrupts can. A priority can be set for each source of maskable interrupts. The CPU accepts an interrupt request with a priority higher than the value in the CPU mask register 93CS44-33 2004-02-10 TMP93CS44/S45 The following (1) to (5) show a flowchart of interrupt processing. (1) Maskable interrupt (Main) EI 1 [1] INTT0 (Level 1) [5] [4] IFF 1 (INTT0 interrupt routine) IFF 2 [2] [3] RETI (2) Non-maskable interrupt (Main) D1 [1] NMI (NMI interrupt routine) IFF 7 [2] [3] [4] IFF 7 RETI (Level 7) [5] During execution of the main program, the CPU accepts an interrupt request. The CPU increments the IFF so that the interrupts of level 1 are not accepted during processing the interrupt routine. DI instruction is executed in the main program, so that the interrupts of only level 7 are accepted. The CPU does not increment the IFF even if the CPU accepts an interrupt request of level 7. (3) Interrupt nesting (Main) EI 3 [1] INTT0 (Level 3) [9] [8] IFF 3 (4) Software interrupt (Main) D1 [1] [5] RETI [6] IFF 4 SWI3 [3] [5] [4] RETI (SWI3 routine) (INTT0 interrupt routine) (INTT1 interrupt routine) IFF 4 [2] [3] INTT1 (Level 4) [7] RETI IFF 5 [4] [2] During processing the interrupts of level 3, the IFF is set to 4. When an interrupt with a level higher than level 4 is generated, the CPU accepts the interrupt with the higher level, causing interrupt processing to nest. The CPU accepts the software interrupt request during DI status (IFF = 7) because of the level 7. The IFF is not changed by the software interrupts. (5) Interrupt sampling timing (INTT0 interrupt routine) (Main) EI 3 [1] INTT0 (Level 3) [8] [7] INTT1 (Level 4) [2] [3] Example: XXX [6] [5] [4] (Underline): Instruction [1], [2], ...: Execution flow RETI RETI If an interrupt with a level higher than the interrupt being processed is generated, the CPU accepts the interrupt with the higher level. The program counter which returns at e is the start address of INTT0 interrupt routine. 93CS44-34 2004-02-10 TMP93CS44/S45 The addresses FFFF00H to FFFFFFH (256 bytes) of the TMP93CS44/S45 are assigned for interrupt vector area. Table 3.4.1 TMP93CS44/S45 Interrupt Table Default Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 - to - Type Interrupt Source Reset or SWI0 instruction SWI 1 instruction Illegal instruction, or SWI2 SWI 3 instruction SWI 4 instruction SWI 5 instruction SWI 6 instruction SWI 7 instruction NMI: NMI pin input INTWD: Watchdog timer INT0: INT0 pin input INT1: INT1 pin input INT4: INT4 pin input INT5: INT5 pin input INT6: INT6 pin input INT7: INT7 pin input INTT0: 8-bit timer 0 INTT1: 8-bit timer 1 INTT2: 8-bit timer 2 INTT3: 8-bit timer 3 INTTR4: 16-bit timer 4 (TREG4) INTTR5: 16-bit timer 4 (TREG5) INTTR6: 16-bit timer 5 (TREG6) INTTR7: 16-bit timer 5 (TREG7) INTTO4: 16-bit timer 4 (Overflow) INTTO5: 16-bit timer 5 (Overflow) INTRX0: Serial receive (Channel 0) INTTX0: Serial send (Channel 0) INTRX1: Serial receive (Channel 1) INTTX1: Serial send (Channel 1) INTAD: AD conversion completion INTS2: Serial bus send and receive (Reserved) to (Reserved) Vector Value "V" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 2 2 0 4 8 C 0 4 8 C 0 4 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H Address Refer to Vector FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H Micro DMA Start Vector - - - - - - - - 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH - to - Nonmaskable Maskable 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 64 68 6C 70 74 78 7C 80 to 00FC FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48H FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H FFFF74H FFFF78H FFFF7CH FFFF80H to H FFFFFCH 93CS44-35 2004-02-10 TMP93CS44/S45 Setting to reset/interrupt vector 1. Reset vector FFFF00H FFFF01H FFFF02H FFFF03H PC<7:0> PC<15:8> PC<23:16> XX The vector base addresses are depended on the products. Type Number TMP93CS44 TMP93CS45 TMP93PS44 TMP93CU44 TMP93CW44 TMP93PW44A FFFF00H Vector Base Address PC Setting Sequence after Reset PC<7:0> Address FFFF00H PC<15:8> Address FFFF01H PC<23:16> Address FFFF02H Notes P27 to P20/A23 to A16 pins input ports with pull-up due to reset. The logic data is "FFH". When port 2 is used as A23 to A16 pins to access the program ROM, set PC<23:16> to "FFH" and the reset vector to "FF0000H to FFFFFFH" (for mainly products without ROM). 2. Interrupt vector (except reset vector) Address refer to vector +0 +1 +2 +3 PC<7:0> PC<15:8> PC<23:16> XX XX: Don't care 93CS44-36 2004-02-10 TMP93CS44/S45 (Setting example) Sets the reset vector: FF0000H, NMI vector: FF9ABCH, INTAD vector: 123456H. ORG DL ORG DL ORG DL ORG LD FFFF00H FF0000H FFFF20H FF9ABCH FFFF78H 123456H FF0000H A, B ; Reset = FF0000H. ; NMI = FF9ABCH. ; INTAD = 123456H. ORG LD FF9ABCH B, C Note: ORG, DL are assembler directives. ORG: Control location counter. DL: Defines long word (32 bits) data. ORG LD 123456H C, A 93CS44-37 2004-02-10 TMP93CS44/S45 3.4.2 Micro DMA In addition to the conventional interrupt processing, the TLCS-900 also has a micro DMA function. When an interrupt is accepted, in addition to an interrupt vector, the CPU receives data indicating whether processing is micro DMA mode or general-purpose interrupt. If micro DMA mode is requested, the CPU performs micro DMA processing. The TLCS-900 can process at very high speed because it has transfer parameters in dedicated registers in the CPU. Since those dedicated registers are assigned as CPU control registers, they can only be accessed by the LDC instruction. (1) Micro DMA operation Micro DMA operation starts when the accepted interrupt vector value matches the micro DMA start vector value. The micro DMA has four channels so that it can be set for up to four types of interrupt source. When a micro DMA interrupt is accepted, data is automatically transferred from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented. If the value in the counter after decrementing is other than 0, micro DMA processing is completed; if the value in the counter after decrementing is 0, general-purpose interrupt processing is performed. 32-bit control registers are used for setting transfer source/destination addresses. However, the TLCS-900 has only 24 address pins for output. A 16-Mbyte space is available for the micro DMA. There are two data transfer modes: one-byte mode and one-word mode. Incrementing, decrementing, and fixing the transfer source/destination address after transfer can be done in both modes. Therefore data can easily be transferred between I/O and memory and between I/Os. For details of transfer modes, see the description of transfer mode registers. The transfer counter has 16 bits, so up to 65536 transfers (the maximum when the initial value of the transfer counter is 0000H) can be performed for one interrupt source by micro DMA processing. When the transfer counter is decremented to "0" after data is transferred with micro DMA, general-purpose interrupt processing is performed. After processing the general-purpose interrupt, starting the interrupts of the same channel restarts the transfer counter from 65536. If necessary, reset the transfer counter. Interrupt sources processed by micro DMA processing are those with the micro DMA start vectors listed in Table 3.4.1. The following timing chart is a micro DMA cycle of the transfer address INC (Increment) mode (Condition: MAX mode, 16-bit bus width for 16 MBytes, 0 waits). 93CS44-38 2004-02-10 1 state DM3 DM4 DM5 DM6 DM7 DM8 DM9 DM10 DM11 DM12 DM13 DM14 (Note 1) (Note 2) (Note 3) (Note 3) (Note 3) DM1 DM2 DM15 DM16 X1 ALE A0 to A15 A0 to A15 AD0 to AD15 D0 to D15 D0 to D15 A0 to A15 D0 to D15 A0 to A15 D0 to D15 A0 to A15 D0 to D15 A16 to A23 Dummy Source address Destination address Dummy Address Dummy Address + 2 Address + 4 RD WR, HWR Figure 3.4.2 Micro DMA Cycle (COUNT 0) 93CS44-39 Note 1: These 2 states are added in the case that the bus width of the source address area is 8 bits or the address starts from an odd number. Note 2: These 2 states are added in the case that the bus width of the destination address area is 8 bits or the address starts from an odd number. Note 3: This may be a dummy cycle with an instruction queue buffer. TMP93CS44/S45 2004-02-10 (Note 1) DM3 DM4 DM5 DM6 DM7 DM8 DM9 DM10 DM11 DM12 DM13 DM14 DM15 (Note 2) (Note 3) (Note 3) DM16 DM1 DM2 X1 ALE A0 to A15 D0 to D15 A0 to A15 AD0 to AD15 D0 to D15 A0 to A15 D0 to D15 A0 to A15 D0 to D15 A16 to A23 Dummy Source address Destination address Dummy Address Dummy Address + 2 Dummy RD WR, HWR (Note 4) (Note 4) DM21 DM22 DM23 DM24 DM25 DM26 DM27 (Note 4) DM18 DM19 DM20 DM17 DM28 DM29 DM30 DM31 DM32 X1 ALE XSP-6 XSP-4 XSP-2 Dummy FFFF00H + V FFFF02H + V Dummy AD0 to AD15 Dummy Figure 3.4.3 Micro DMA Cycle (COUNT = 0) DM34 DM35 DM36 DM37 Address Address + 2 93CS44-40 RD WR, HWR DM33 X1 ALE AD0 to AD15 Dummy RD WR, HWR Note 1: These 2 states are added in the case that the bus width of the source address area is 8 bits or the address starts from an odd number. Note 2: These 2 states are added in the case that the bus width of the destination address area is 8 bits or the address starts from an odd number. Note 3: This be a dummy cycle with an instruction queue buffer. TMP93CS44/S45 2004-02-10 Note 4: These 2 states are added in the case of the bus width of stack address area is 8 bits or stack pointer starts from an odd number. TMP93CS44/S45 (2) Register configuration (CPU control register) Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 Channel 1 DMAS1 DMAD1 DMAC1 DMAM1 Channel 2 DMAS2 DMAD2 DMAC2 DMAM2 Channel 3 DMAS3 DMAD3 DMAC3 DMAM3 8 bits 16 bits 32 bits Transfer source address register 3 Transfer destination address register 3 Transfer counter register 3 Transfer mode register 3 Transfer source address register 2 Transfer destination address register 2 Transfer counter register 2 Transfer mode register 2 Transfer source address register 1 Transfer destination address register 1 Transfer counter register 1 Transfer mode register 1 Transfer source address register 0 Transfer destination address register 0 Transfer counter register 0 (1 to 65536) Transfer mode register 0 (Use only lower 24 bits.) These control register can not be set only "LDC cr, r" instruction. Example: LD LDC LD LDC LD LDC LD LDC XWA, 100H DMAS0, XWA XWA, 50H DMAD0, XWA WA, 40H DMAC0, WA A, 05H DMAM0, A 93CS44-41 2004-02-10 TMP93CS44/S45 (3) Transfer mode register details (DMAM0 to DMAM3) 0 0 0 0 Mode Note: When setting values for this register, set the upper 4 bits to 0. Z 0 = byte transfer, 1 = word transfer 0 0 0 Z Transfer destination address INC mode............................ for I/O to memory (DMADn+) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INT. Transfer destination address DEC mode .......................... for I/O to memory (DMADn-) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INT. Transfer source address INC mode .................................. for memory to I/O (DMADn) (DMASn+) DMACn DMACn - 1 if DMACn = 0 then INT. Transfer source address DEC mode................................. for memory to I/O (DMADn) (DMASn-) DMACn DMACn - 1 if DMACn = 0 then INT. Fixed address mode ......................................................... I/O to I/O (DMADn) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INT. Counter mode................................................................... for interrupt counter DMASn DMASn + 1 DMACn DMACn - 1 if DMACn = 0 then INT. Execution time (Min) at 20 MHz 16 states (1.6 s) 16 states (1.6 s) 16 states (1.6 s) 16 states (1.6 s) 16 states (1.6 s) 11 states (1.1 s) 0 0 1 Z 0 1 0 Z 0 1 1 Z 1 0 0 Z 1 0 1 1 (1 states = 100 ns at 20 MHz, High-frequency mode) Note 1: n: Corresponds to micro DMA channels 0 to 3. DMADn+/DMASn+: Post-increment (Increments register value after transfer.) DMADn-/DMASn-: Post-decrement (Decrement register value after transfer.) Note 2: Execution time: When setting source address/destination address area to 16-bit bus, 0 waits. Clock condition: fc = 20 MHz, clock gear: 1 (fc) Note 3: Do not use the codes other than the above mentioned codes for transfer mode register. 93CS44-42 2004-02-10 TMP93CS44/S45 3.4.3 Interrupt Controller Figure 3.4.4 is a block diagram of the interrupt circuits. The left half of the diagram shows the interrupt controller; the right half includes the CPU interrupt request signal circuit and the halt release signal circuit. Each interrupt channel (Total of 24 channels) in the interrupt controller has an interrupt request flip-flop, interrupt priority setting register, and a register for storing the micro DMA start vector. The interrupt request fip-flop is used to latch interrupt requests from peripheral devices. The flip-flop is cleared to 0 at reset, when the CPU reads the interrupt channel vector after the acceptance of interrupt, or when the CPU executes an instruction that clears the interrupt of that channel (Writes 0 in the clear bit of the interrupt priority setting register). For example, to clear the INT0 interrupt request, set the register after the DI instruction as follows. INTE0AD - - - - 0 - - - B The status of the interrupt request flip-flop is detected by reading the clear bit. Detects whether there is an interrupt request for an interrupt channel. The interrupt priority can be set by writing the priority in the interrupt priority setting register (e.g., INTE0AD, INTE45 etc.) provided for each interrupt source. Interrupt levels to be set are from 1 to 6. Writing 0 or 7 as the interrupt priority disables the corresponding interrupt request. The priority of the non-maskable interrupt ( NMI pin, watchdog timer etc.) is fixed to 7. If interrupt requests with the same interrupt level are generated simultaneously, interrupts are accepted in accordance with the default priority (the smaller the vector value, the higher the priority). The interrupt controller sends the interrupt request with the highest priority among the simultaneous interrupts and its vector address to the CPU. The CPU compares the priority value 93CS44-43 2004-02-10 Interrupt controller Interrupt request flip-flop S Q 1 Interrupt request signal to CPU IFF<2:0> 1 7 INTRQ2 to 0 3 Interrupt vector read D0 D1 24 D2 D3 Interrupt vector generation D4 D5 D6 If INTRQ2 to 0 IFF2 to 0 then 1. 3 3 6 Interrupt enable flag on CPU side RESET RESET R Interrupt vecror V read CPU NMI INTWD Interrupt level detect EI 1 to EI 7 DI Interrupt request signal Priority setting register Dn Dn + 1 D Q Dn + 2 CLR Interrupt request F/F S Q Dn + 3 (Highese priority = 7) RESET V = 20H V = 24H Decoder Y1 A Y2 Y3 B Y4 C Y5 Y6 6 Priority encoder 1 2 A 3 Highest B priority C 4 interrupt 5 level select 6 7 INT0 R Interrupt request flip-flop read During IDLE1 During STOP Figure 3.4.4 Block Diagram of Interrupt Controller 93CS44-44 5 Micro DMA start vector setting register Halt release RESET INT0 NMI INT1 INT4 INT5 INT6 INT7 INTT0 INTT1 INTT2 INTT3 INTTR4 INTTR5 INTTR6 INTTR7 INTTO4 INTTO5 INTRX0 INTTX0 INTRX1 INTTX1 INTAD INTS2 4 5 5 Match detect 4 input OR Interrupt request clear Dn + 3 Interrupt request V read V = 28H V = 2CH V = 30H V = 34H V = 38H V = 3CH V = 40H V = 44H V = 48H V = 4CH V = 50H V = 54H V = 58H V = 5CH V = 60H V = 64H V = 68H V = 6CH V = 70H V = 74H V = 78H V = 7CH Micro DMA request TMP93CS44/S45 D4 D3 D Q D2 D1 CLR D0 RESET 2 DMA0V DMA1V DMA2V DMA3V 0 A 1 2 B 3 Micro DMA channel priorty encoder 2004-02-10 2 Micro DMA channel specification TMP93CS44/S45 (1) Interrupt priority setting register Symbol INTE0AD Address 0070H 7 IADC R/W 0 I5C R/W 0 I7C R/W 0 IT1C R/W 0 IT3C R/W 0 IT5C R/W 0 IT7C R/W 0 ITO5C R/W 0 ITX0C R/W 0 ITX1C R/W 0 I1C R/W 0 5 INTAD IADM2 IADM1 W 0 0 INT5 I5M2 I5M1 W 0 0 INT7 I7M2 I7M1 W 0 0 INTT1 (Timer 1) IT1M2 IT1M1 W 0 0 INTT3 (Timer 3) IT3M2 IT3M1 W 0 0 INTTR5 (TREG5) IT5M2 IT5M1 W 0 INTTR7 (TREG7) IT7M2 IT7M1 W 0 0 INTTO5 ITO5M2 ITO5M1 W 0 0 INTTX0 ITX0M2 ITX0M1 W 0 0 INTTX1 ITX1M2 ITX1M1 W 0 0 INT1 I1M2 I1M1 W 0 0 6 4 IADM0 0 I5M0 0 I7M0 0 IT1M0 0 IT3M0 0 IT5M0 0 IT7M0 0 ITO5M0 0 ITX0M0 0 ITX1M0 0 I1M0 0 3 I0C R/W 0 I4C R/W 0 I6C R/W 0 IT0C R/W 0 IT2C R/W 0 IT4C R/W 0 IT6C R/W 0 ITO4C R/W 0 IRX0C R/W 0 IRX1C R/W 0 IS2C R/W 0 (Prohibit read-modify-write) 2 INT0 I0M2 0 INT4 I4M2 0 INT6 I6M1 W 0 0 INTT0 (Timer 0) IT0M2 IT0M1 W 0 0 INTT2 (Timer 2) IT2M2 IT2M1 W 0 0 INTTR4 (TREG4) IT4M2 IT4M1 W 0 0 INTTR6 (TREG6) IT6M2 IT6M1 W 0 0 INTTO4 ITO4M2 ITO4M1 W 0 0 INTRX0 IRX0M2 IRX0M1 W 0 0 INTRX1 IRX1M2 IRX1M1 W 0 0 INTS2 IS2M2 IS2M1 W 0 0 I6M2 I6M0 0 IT0M0 0 IT2M0 0 IT4M0 0 IT6M0 0 ITO4M0 0 IRX0M0 0 IRX1M0 0 IS2M0 0 I4M1 W 0 I4M0 0 I0M1 W 0 I0M0 0 1 0 Interrupt source Bit symbol Read/Write After reset INTE45 0071H INTE67 0072H INTET10 0073H INTET32 0074H INTET54 0075H INTET76 0076H INTEO54 0077H INTES0 0078H INTES1 0079H INTE1S2 007AH IxxM2 0 0 0 0 1 1 1 1 IxxC 0 1 IxxM1 0 0 1 1 0 0 1 1 IxxM0 0 1 0 1 0 1 0 1 Function (Write) Prohibits interrupt request. Sets interrupt request level to 1. Sets interrupt request level to 2. Sets interrupt request level to 3. Sets interrupt request level to 4. Sets interrupt request level to 5. Sets interrupt request level to 6. Prohibits interrupt request. Function (Write) Clears interrupt request flag. Don't care Function (Read) Indicates no interrupt request. Indicates interrupt request. Note 1: Read-modify-write is prohibited. Note 2: Note about clearing interrupt request flag The interrupt request flag of INTRX0, INTRX1 are not cleared by writing "00" to IXXC because of they are level interrupts. They can be cleared only by resetting or reading SCBUFn. Figure 3.4.5 Interrupt Priority Setting Register 93CS44-45 2004-02-10 TMP93CS44/S45 (2) External interrupt control Interrupt Input Mode Control Register 7 IIMC (007BH) Bit symbol Read/Write After reset Function Prohibit readmodifywrite 6 5 - W 0 Always write "0". 4 3 2 I0IE 0 1: INT0 input enable 1 I0LE W 0 0: INT0 edge mode 1: INT0 level mode 0 NMIREE 0 1: Can be accepted in NMI rising edge. INT0 input enable (Note 1) 0 INT0 disable (P35 function only) 1 Input enable NMI rising edge enable 0 1 Interrupt request generation at falling edge Interrupt request generation at rising/falling edge Note 1: The INT0 pin can also be used for standby release as described later. Even if the pin is not used for standby release, setting this register to "0" maintains the port function during standby mode. Case of changing from level to edge for INT0 pin mode ( INT0 level enable (Note 2) 0 Rising edge detect interrupt 1 High level interrupt Note 2: ; INT0 disable, clean the request flag. ; Change from level to edge. ; Set interrupt level "n" for INT0, clear the request flag. Note 3: Note 4: IIMC Figure 3.4.6 Interrupt Input Mode Control Register Table 3.4.2 Setting of External Interrupt Pin Functions Interrupt NMI Shared Pin NMI Mode Falling edge Setting method IIMC (Dedicated pin) Falling and rising IIMC INT0 P35 Level INT1 P40 Rising edge Rising edge INT4 P42 Falling edge INT5 P43 Rising edge Rising edge INT6 P45 Falling edge INT7 P46 Rising edge 93CS44-46 2004-02-10 TMP93CS44/S45 (3) Micro DMA start vector When the CPU reads the interrupt vector after accepting an interrupt, it simultaneously compares the interrupt vector (Bits 2 to 6 of the interrupt vector) with each channel's micro DMA start vector. When the two match, the interrupt from the channel whose value matched is processed in micro DMA mode. If the interrupt vector matches more than one channel, the channel with the lower channel number has a higher priority. Micro DMA0 Start Vector 7 DMA0V (007CH) Prohibit readmodifywrite Bit symbol Read/Write After reset Function 0 0 6 5 4 DMA0V4 3 DMA0V3 2 DMA0V2 W 0 1 DMA0V1 0 0 DMA0V0 0 Micro DMA channel 0 processed by matching bits 2 to 6 of the interrupt vector. Micro DMA1 Start Vector 7 DMA1V (007DH) Prohibit readmodifywrite Bit symbol Read/Write After reset Function 0 0 6 5 4 DMA1V4 3 DMA1V3 2 DMA1V2 W 0 1 DMA1V1 0 0 DMA1V0 0 Micro DMA channel 1 processed by matching bits 2 to 6 of the interrupt vector. Micro DMA2 Start Vector 7 DMA2V (007EH) Prohibit readmodifywrite Bit symbol Read/Write After reset Function 0 0 6 5 4 DMA2V4 3 DMA2V3 2 DMA2V2 W 0 1 DMA2V1 0 0 DMA2V0 0 Micro DMA channel 2 processed by matching bits 2 to 6 of the interrupt vector. Micro DMA3 Start Vector 7 DMA3V (007FH) Prohibit readmodifywrite Bit symbol Read/Write After reset Function 0 0 6 5 4 DMA3V4 3 DMA3V3 2 DMA3V2 W 0 1 DMA3V1 0 0 DMA3V0 0 Micro DMA channel 3 processed by matching bits 2 to 6 of the interrupt vector. Figure 3.4.7 Micro DMA Start Vector Register 93CS44-47 2004-02-10 TMP93CS44/S45 (4) Notes The instruction execution unit and the bus interface unit of this CPU operate independently of each other. Therefore, if the instruction used to clear an interrupt request flag of an interrupt is fetched before the interrupt is generated, it is possible that the CPU might execute the fetched instruction to clear the interrupt request flag while reading the interrupt vector after accepting the interrupt. To avoid the above occurring, clear the interrupt request flag by entering the instruction to clear the flag after the DI instruction. In the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing instruction and following more than one instruction are executed. When EI instruction is placed immediately after clearing instruction, an interrupt becomes enable before interrupt request flags are cleared. In the case of changing the value of the interrupt mask register 93CS44-48 2004-02-10 TMP93CS44/S45 3.5 Functions of Ports The TMP93CS44 has 62 bits for I/O ports. The TMP93CS45 has 44 bits for I/O ports because Port 0, Port 1, P30, and P31 are dedicated pins for AD0 to AD7, AD8 to AD15 (or A8 to A15), RD , and WR . These port pins have I/O functions for the built-in CPU and internal I/Os as well as general-purpose I/O port functions. Table 3.5.1 lists the function of each port pin. Table 3.5.2 lists I/O registers and specification. Table 3.5.1 Functions of Ports (PU = with programmable pull-up resistor) Port Name Port 0 Port 1 Port 2 Port 3 Pin Name P00 to P07 P10 to P17 P20 to P27 P30 P31 P32 P33 P34 P35 Pin Number 8 8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 4 1 1 1 1 1 1 1 1 1 7 Direction I/O I/O I/O Output Output I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O R - - PU - - PU - - - - - - - - - - - - - - PU PU PU PU PU PU - - - - Direction Setting Unit Bit Bit Bit (fixed) (fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit (fixed) (fixed) (fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Pin Name for Built-in Function AD0 to AD7 AD8 to AD15/A8 to A15 A0 to A7/A16 to A23 RD WR HWR /SCK SO/SDA SI/SCL INT0 TI0/INT1 TO3 TI4/INT4 TI5/INT5 TO4 TI6/INT6 TI7/INT7 TO6 AN0 to AN2 AN3/ ADTRG AN4 to AN7 TXD0 RXD0 SCLK0/ CTS0 TXD1 RXD1 SCLK1/ CTS1 XT1 XT2 WAIT (High current output) Port 4 P40 P41 P42 P43 P44 P45 P46 P47 Port 5 P50 to P52 P53 P54 to P57 Port 6 P60 P61 P62 P63 P64 P65 P66 P67 Port 7 P70 P71 to P77 (High current output) 93CS44-49 2004-02-10 TMP93CS44/S45 Table 3.5.2 I/O Registers and Specification (1/2) Port Port 0 Name P00 to P07 Specification Input port (Note 1) Output port (Note 1) AD0 to AD7 bus I/O Register Pn x x x x x x x 0 1 x 0 0 x 1 0 x x 0 1 x x x x x x x x x x x x x x x x x x x x x None 0 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 None None PnCR 0 1 x 0 1 0 1 0 0 1 0 1 PnFC None 0 0 1 1 0 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 0 1 0 x 0 1 None None 0 0 1 Port 1 P10 to P17 Input port (Note 1) Output port (Note1) AD8 to AD15 bus (Note 2) AD8 to AD15 output (Note 2) Port 2 P20 to P27 Input port (without pull up) Input port (with pull up) Output port A0 to A7 output (Note 1) A16 to A23 output Port 3 P30 Output port (Note 1) Outputs RD only when accessing external space Always outputs RD P31 Output port (Note 1) Outputs WR only when accessing external space P32 Input port SCK input (without pull up) Input port SCK input (with pull up) Output port HWR output ( SCK output ( X: Don't care, n: Port number Note 1: In the TMP93CS45, these functions are not available. Note 2: In the TMP93CS45, these functions are fixed depending on the value of the AM8/ AM16 pin. Note 3: Using P35 pin as INT0, IIMC register has to be set enable interrupt. 93CS44-50 2004-02-10 TMP93CS44/S45 Table 3.5.2 I/O Registers and Specification (2/2) Port Port 4 Name P44 Input port Output port TO4 output P45 P46 P47 Specification I/O Register Pn x x x x x x x x x x x x 0 1 x x 0 1 x 0 1 x x 0 1 x x 0 1 x 0 1 x x x x x x x x x 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 1 0 0 1 0 1 None None 0 0 0 1 None 0 0 0 1 0 0 0 1 None PnCR 0 1 1 0 1 0 1 0 1 1 PnFC 0 0 1 Input port/TI6/INT6 input Output port Input port/TI7/INT7 input Output port Input port Output port TO6 output None 0 0 1 None 0 0 0 1 Port 5 Port 6 P50 to P57 P60 Input port AN0 to AN7 input (Note 4) Input port (without pull up) Input port (with pull up) Output port TXD0 output P61 Input port/RXD0 input (without pull up) Input port/RXD0 input (with pull up) Output port P62 Input port/SCLK0/ CTS0 input (without pull up) Input port/SCLK0/ CTS0 input (with pull up) Output port SCLK0 output P63 Input port (without pull up) Input port (with pull up) Output port TXD1 output (Note 3) P64 Input port/RXD1 input (without pull up) Input port/RXD1 input (with pull up) Output port P65 Input port/SCLK1/ CTS1 input (without pull up) Input port/SCLK1/ CTS1 input (with pull up) Output port SCLK1 output P66, P67 Input port Output port (Note 5) XT1/2 (Note 6) Port 7 P70 P71 to P77 Input port/ WAIT input Output port Input port Output port X: Don't care, n: Port number Note 4: Using P50 to P57 pins as input channels for the AD converter, the channels are selected by ADMOD1 93CS44-51 2004-02-10 TMP93CS44/S45 Resetting makes the port pins listed below function as general-purpose I/O ports. I/O pins programmable for input or output are set to input ports except P66/XT1, P67/XT2. To set port pins for built-in functions, a program is required. Since the TMP93CS45 needs external ROMs, some ports are permanently assigned for memory interface. * * P00 to P07 P10 to P17 AD0 to AD7 AD8 to AD15 (or A8 to A15) * * P30 P31 RD WR 93CS44-52 2004-02-10 TMP93CS44/S45 3.5 3.5.1 Port 0 (P00 to P07) Port 0 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis using the control register P0CR. Resetting sets all bits of P0CR to 0 and sets port 0 to input mode. Figure 3.5.3 shows the registers for port 0. In addition to functioning as a general-purpose I/O port, port 0 also shares functions as an address data bus (AD0 to AD7). To access external memory, port 0 functions as an address data bus (AD0 to AD7) and all bits of the control register P0CR are set to 0. With the TMP93CS45, which needs external ROMs, port 0 always functions as an address data bus (AD0 to AD7) regardless of the value set in control register P0CR. Reset Direction control (on bit basis) P0CR write Internal data bus Output latch Output buffer P0 write Port 0 P00 to P07 (AD0 to AD7) S S B Selector A P0 read B Selector A Figure 3.5.1 Port 0 93CS44-53 2004-02-10 TMP93CS44/S45 3.5.2 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis using control register P1CR and function register P1FC. Resetting sets all bits of output latch P1, control register P1CR, and function register P1FC to 0 and sets port 1 to input mode. Figure 3.5.3 shows the registers for port 1. In addition to functioning as a general-purpose I/O port, port 1 also shares functions as an address data bus (AD8 to AD15) or an address bus (A8 to A15). With the TMP93CS45, which needs external ROMs, port 1 always functions as an address data bus (AD8 to AD15) (the case of AM8/ AM16 = 0), as an address bus (A8 to A15) (the case of AM8/ AM16 = 1) regardless of the value set in control register P1CR. Reset Direction control (on bit basis) P1CR write Internal data bus Function control (on bit basis) P1FC write Output latch Output buffer P1 write S B Selector A P1 read Port 1 P10 to P17 (AD8 to AD15/A8 to A15) Figure 3.5.2 Port 1 93CS44-54 2004-02-10 TMP93CS44/S45 Port 0 Register 7 P0 (0000H) Bit symbol Read/Write After reset P07 6 P06 5 P05 4 P04 R/W 3 P03 2 P02 1 P01 0 P00 Input mode (Output latch register becomes undefined.) Port 0 Control Register 7 P0CR (0002H) Prohibit readmodifywrite Bit symbol Read/Write After reset Function 0 0 0 0 P07C 6 P06C 5 P05C 4 P04C W 3 P03C 0 2 P02C 0 1 P01C 0 0 P00C 0 0: Input 1: Output (at external access, port 0 becomes AD7 to AD0 and P0CR is set to "0".) Port 0 I/O setting 0 Input 1 Output Port 1 Register 7 P1 (0001H) Bit symbol Read/Write After reset P17 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Input mode (Output latch register is set to "0".) Port 1 Control Register 7 P1CR (0004H) Prohibit readmodifywrite Bit symbol Read/Write After reset Function 0 0 0 0 P17C 6 P16C 5 P15C 4 P14C W 3 P13C 0 2 P12C 0 1 P11C 0 0 P10C 0 < Port 1 Function Register 7 P1FC (0005H) Prohibit readmodifywrite Bit symbol Read/Write After reset Function 0 0 0 0 01: Output P1FC/P1CR = 00: Input P17F 6 P16F 5 P15F 4 P14F W 3 P13F 0 2 P12F 0 1 P11F 0 11: A15 to A8 0 P10F 0 10: AD15 to AD8 Port 1 function setting P1FC Input port Output port Note: Figure 3.5.3 Registers for Port 0 and Port 1 93CS44-55 2004-02-10 TMP93CS44/S45 3.5.3 Port 2 (P20 to P27) Port 2 is an 8-bit general-purpose I/O port. I/O can be set on bit basis using the control register P2CR and function register P2FC. All bits of the output latch P2 is set to 1 by reset, and all bits of P2CR and P2FC are cleared to 0. Port 2 becomes the input mode with the pull-up resistor. In addition to functioning as a general-purpose I/O port, port 2 also shares functions as an address data bus (A0 to A7) and an address bus (A16 to A23). Using port 2 as address bus (A0 to A7 or A16 to A23), write 0 to output latches and be off the programmable pull-up resistor. A16 to A23 B Selector A0 to A7 Reset A S Direction control (on bit basis) P2CR write Internal data bus Function control (on bit basis) S P2FC write B Selector Output latch A Output buffer P-ch Programmable pull up Port 2 P20 to P27 (A0 to A7/A16 to A23) P2 write S B Selector A P2 read Figure 3.5.4 Port 2 93CS44-56 2004-02-10 TMP93CS44/S45 Port 2 Register 7 P2 (0006H) Bit symbol Read/Write After reset Note 1: P27 6 P26 5 P25 4 P24 R/W 3 P23 2 P22 1 P21 0 P20 Input mode (Output latch register is set to "1".) When port 2 is used in the input mode, P2 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. Port 2 Control Register 7 P2CR (0008H) Prohibit readmodifywrite Bit symbol Read/Write After reset Function 0 0 0 0 P27C 6 P26C 5 P25C 4 P24C W 3 P23C 0 2 P22C 0 1 P21C 0 0 P20C 0 < Port 2 Function Register 7 P2FC (0009H) Prohibit readmodifywrite Bit symbol Read/Write After reset Function 0 0 0 0 01: Output P2FC/P2CR = 00: Input P27F 6 P26F 5 P25F 4 P24F W 3 P23F 0 10: A7 to A0 2 P22F 0 1 P21F 0 11: A23 to A16 0 P20F 0 Port 2 function setting P2FC 0 Input port Output port 1 Address bus (A7 to A0) Address bus (A23 to A16) 0 1 Note 2: Figure 3.5.5 Registers for Port 2 93CS44-57 2004-02-10 TMP93CS44/S45 3.5.4 Port 3 (P30 to P35) Port 3 is an 6-bit general-purpose I/O port. I/O can be set on a bit basis, but note that P30 and P31 are used for output only. I/O is set using control register P3CR and function register P3FC. Resetting sets all bits of output latch P3 to 1. All bits of control register P3CR (bits 0 and 1 are unused), and function register P3FC are set to 0. Resetting also outputs 1 from P30 and P31. In addition to functioning as a general-purpose I/O port, port 3 also shares functions as an I/O for the CPU's control/status signal and serial bus interface. With the TMP93CS44, when P30 pin is defined as RD signal output mode ( 93CS44-58 2004-02-10 TMP93CS44/S45 (1) P30 ( RD ), P31 ( WR ) Reset for TMP93CS45 Function control (on bit basis) Internal data bus P3FC write S Output latch P3 write S A Selector Output buffer B RD , WR P30 ( RD ) P31 ( WR ) P3 read (2) P32 ( HWR /SCK) Reset Direction control (on bit basis) P3CR write Function control (on bit basis) P3FC Function control (on bit basis) P3FC HWR P-ch Programmable pull up S A S A Selector SCK S B B Selector B Output buffer P32 ( HWR /SCK) P3 write Selector P3 read SCK A Figure 3.5.6 Port 3 (P30, P31, P32) 93CS44-59 2004-02-10 TMP93CS44/S45 (3) P33 (SDA/SO), P34 (SCL/SI) Reset Direction control (on bit basis) P3CR write Function control (on bit basis) Internal data bus P3FC write S Output latch A S Selector P33 (SDA/SO) P34 (SCL/SI) P3 write SDA/SO out SCL out B S B Selector Open-drain possible ODE P3 read SDA in SCL/SI in A Figure 3.5.7 Port 3 (P33 and P34) (4) P35 (INT0) Port 35 is a general-purpose I/O port, and also used as an INT0 pin for external interrupt request input. Reset Direction control (on bit basis) P3CR write Internal data bus S Output latch P35 (INT0) P3 write S B Selector A Level/edge detect IIMC P3 read INT0 interrupt Figure 3.5.8 Port 3 (P35) 93CS44-60 2004-02-10 TMP93CS44/S45 Port 3 Register 7 P3 (0007H) Bit symbol Read/Write After reset Function Note 1: 1 1 Input mode 1 6 5 P35 4 P34 3 P33 R/W 2 P32 1 Input mode (pulled up) 1 P31 1 0 P30 1 Output mode When port 32 is used in the input mode, P3 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. Port 3 Control Register 7 P3CR (000AH) Prohibit readmodifywrite Bit symbol Read/Write After reset Function 0 0 0: Input 6 5 P35C 4 P34C W 3 P33C 0 1: Output 2 P32C 0 1 0 I/O setting 0 Input 1 Output Port 3 Function Register 7 P3FC (000BH) Prohibit readmodifywrite Bit symbol Read/Write After reset Function 6 P32M W 0 0: HWR 1: SCK 5 4 P34F 0 0: Port 1: SCL/SI 3 P33F 0 2 P32F W 0 1 P31F 0 0: Port 1: WR 0 P30F 0 0: Port 1: RD 0: Port 0: Port 1: SDA/SO 1: P32M P34 function setting (Note 2) P31 ( RD ) function setting 1 "1" output RD output only for external access P33 function setting (Note 2) 1 P31 ( WR ) function setting 1 "1" output WR output only for external 1 Figure 3.5.9 Registers for Port 3 93CS44-61 2004-02-10 TMP93CS44/S45 3.5.5 Port 4 (P40 to P47) Port 4 is a 8-bit general-purpose I/O port. I/O can be set on bit basis. Resetting sets port 4 to the input port. In addition to functioning as a general-purpose I/O port, port 4 also shares functions as an input for 8-bit timer 0 clock, 16-bit timer 4 and 5 clocks, an output for 8-bit timer F/F 3, 16-bit timer F/F 4 and 6 output. Writing 1 in the corresponding bit of the port 4 function register (P4FC) enables output of the timer. (1) P40 and P41 Reset Direction control (on bit basis) P4CR write S Output latch P40 (TI0/INT1) S B Selector A P4 write P4 read TI0, INT1 Reset Internal data bus Direction control (on bit basis) P4CR write Function control (on bit basis) P4FC write S Output latch S A Selector B B Selector A S P4 write Timer F/F OUT (TO3: Timer 3) P41 (TO3) P4 read Figure 3.5.10 Port 4 (P40 and P41) 93CS44-62 2004-02-10 TMP93CS44/S45 (2) P42 to P47 Reset Direction control (on bit basis) P4CR write S Output latch P42 (TI4/INT4) P43 (TI5/INT5) P45 (TI6/INT6) P46 (TI7/INT7) S B Selector A P4 write P4 read TI4, INT4 TI5, INT5 TI6, INT6 TI7, INT7 Internal data bus Reset Direction control (on bit basis) P4CR write Function control (on bit basis) P4FC write S Output latch S A Selector B B Selector A S P4 write Timer F/F OUT TO4: Timer 4 TO6: Timer 5 P44 (TO4) P47 (TO6) P4 read Figure 3.5.11 Port 4 (P42 to P47) 93CS44-63 2004-02-10 TMP93CS44/S45 Port 4 Register 7 P4 (000CH) Bit symbol Read/Write After reset 1 1 1 1 Input mode P47 6 P46 5 P45 4 P44 R/W 3 P43 1 2 P42 1 1 P41 1 0 P40 1 Port 4 Control Register 7 P4CR (000EH) Prohibit readmodifywrite Bit symbol Read/Write After reset Function 0 0 0 0 0: Input P47C 6 P46C 5 P45C 4 P44C W 3 P43C 0 1: Output 2 P42C 0 1 P41C 0 0 P40C 0 Port 4 I/O setting 0 Input 1 Output Port 4 Function Register 7 P4FC (0010H) Prohibit readmodifywrite Bit symbol Read/Write After reset Function P47F W 0 0: Port 1: TO6 6 5 4 P44F W 0 0: Port 1: TO4 3 2 1 P41F W 0 0: Port 1: TO3 0 Setting P41 as TO3 P4FC 1 1 1 1 1 1 For example, when it is used as an input port, the input signal for port is inputted to 8- or 16-bit timer as a timer input. Figure 3.5.12 Register for Port 4 93CS44-64 2004-02-10 TMP93CS44/S45 3.5.6 Port 5 (P50 to P57) Port 5 is an 8-bit input port, also used as an analog input pin for the internal AD converter. Additionally, P53 is also used as an analog conversion external trigger input pin ( ADTRG ). Port 5 Port 5 read P50 to P52 (AN0 to AN2) P53 (AN3/ ADTRG ) P54 to P57 (AN4 to AN7) Internal data bus Conversion result register AD read AD converter Channel selector ADTRG Only for P53 function Figure 3.5.13 Port 5 Port 5 Register 7 P5 (000DH) Bit symbol Read/Write After reset P57 6 P56 5 P55 4 P54 R 3 P53 2 P52 1 P51 0 P50 Input mode Figure 3.5.14 Register for Port 5 Note: The input channel selection of AD converter is set by AD converter mode register ADMOD1. 93CS44-65 2004-02-10 TMP93CS44/S45 3.5.7 Port 6 (P60 to P67) * Ports 60 to 65 Ports 60 to 65 are a 6-bit general-purpose I/O port. I/Os can be set on a bit basis. Resetting sets P60 to P65 to an input port and connects a pull-up resistor. It also sets all bits of the output latch register to 1. In addition to functioning as a general-purpose I/O port, P60 to P65 can also share function as an I/O for serial channels 0 and 1. Writing "1" in the corresponding bit of the Port 6 function register (P6FC) enables this function. Resetting sets the function register value to 0 and sets all bits to input ports. * Port 66 and port 67 Port 66 and port 67 are a 2-bit general-purpose I/O port. I/Os can be set on a bit basis. The output buffer for P66, P67 is an open-drain type buffer. Resetting outputs high-impedance (High-Z) because output latch and control register are set to 1. In addition to functioning as a general-purpose I/O port, P66, P67 can also function as a low-frequency oscillator connecting pin (XT1, XT2) for dual clock mode. The dual clock function can be set by programming system clock control registers SYSCR0, SYSCR1. (1) Port 60 (TXD0) and port 63 (TXD1) Port 60 and port 63 also function as serial channel TXD output pins in addition to I/O ports. They have a programmable open-drain function. Reset Direction control (on bit basis) P6CR write Internal data bus Function control (on bit basis) P-ch Programmable pull up S A Selector B S B Selector A P60 (TXD0) P63 (TXD1) P6FC write S Output latch P6 write TXD0, TXD1 Open-drain possible ODE P6 read Figure 3.5.15 Ports 60 and 63 93CS44-66 2004-02-10 TMP93CS44/S45 (2) Port 61 (RXD0) and port 64 (RXD1) Port 61 and port 64 are I/O ports, and also used as RXD input pins for serial channels. Reset Direction control (on bit basis) Internal data bus P-ch Programmable pull up P61 (RXD0) P64 (RXD1) S B Selector A P6CR write S Output latch P6 write P6 read RXD0, RXD1 Figure 3.5.16 Port 61 and Port 64 (3) Port 62 ( CTS0 /SCLK0) and port 65 ( CTS1 /SCLK1) Port 62 and port 65 are I/O ports, and also used as a CTS input pin and as a SCLK I/O pin for serial channels. Reset Direction control (on bit basis) P6CR write Internal data bus Function control (on bit basis) P6FC write S Output latch P-ch Programmable pull up S A Selector B S B Selector A P62 (SCLK0/ CTS0 ) P65 (SCLK1/ CTS1 ) P6 write SCLK0 OUT SCLK1 OUT P6 read CTS0 , CTS1 SCLK0, SCLK1 Figure 3.5.17 Port 62 and Port 65 93CS44-67 2004-02-10 TMP93CS44/S45 (4) Port 66 (XT1) and port 67 (XT2) Port 66 and port 67 are general purpose I/O ports. It is also used as a low-frequency oscillator connecting pin. Reset BUS6 S Direction control (on bit basis) P6CR write S Output latch Output buffer (Open-drain output) Low-frequency oscillation enable BUS6 P66 (XT1) P6 write S Internal data bus BUS6 B Selector A P6 read S Direction control (on bit basis) P6CR write S Output latch (ON at "1") BUS7 BUS7 P67 (XT2) Output buffer (Open-drain output) Low-frequency clock (fs) P6 write S BUS7 B Selector A P6 read Figure 3.5.18 Port 66 to Port 67 93CS44-68 2004-02-10 TMP93CS44/S45 Port 6 Register 7 P6 (0012H) Bit symbol Read/Write After reset 1 1 1 1 Output mode Note 1: P67 6 P66 5 P65 4 P64 R/W 3 P63 1 2 P62 1 1 P61 1 0 P60 1 Input mode When P6 is used in the input mode, P6 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. Port 6 Control Register 7 P6CR (0014H) Prohibit readmodifywrite Bit symbol Read/Write After reset Function 1 1 0 0: Input 0 P67C 6 P66C 5 P65C 4 P64C W 3 P63C 0 1: Output 2 P62C 0 1 P61C 0 0 P60C 0 Note: Output buffer for port 66, 67 is an open-drain output type. Port 6 I/O setting 0 Input 1 Output Port 6 Function Register 7 P6FC (0016H) Prohibit readmodifywrite Bit symbol Read/Write After reset Function 6 5 P65F W 0 0: Port 1: SCLK1 4 3 P63F W 0 0: Port 1: TXD1 2 P62F 0 0: Port 1: SCLK0 1 0 P60F W 0 0: Port 1: TXD0 P63 TXD1 output setting (Note) P6FC P60 TXD0 output setting (Note) P6FC P65 SCLK1 output setting P6FC P62 SCLK0 output setting P6FC Note 2: To set the TXD pin to open drain, write "1" in bit0 (for TXD0 pin) or bit1 (for TXD1 pin) of the ODE register. P61/RXD0, P64/RXD1 pins do not have a register changing port/function. When using as input ports, the serial receive data is input to SIO. Note 3: Notes on using low-frequency oscillation circuit. To connect a low frequency resonator to port 66, 67, it is necessary to set the following procedures to reduce the consumption power supply. (Connecting to a resonator) Set P6CR Figure 3.5.19 Register for Port 6 93CS44-69 2004-02-10 TMP93CS44/S45 3.5.8 Port 7 (P70 to P77) Port 7 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis. Port 7 can output large current and drive LED directly. In addition to I/O port, port 70 also shares functions as WAIT input pin. Resetting sets the function register P7CR to 0, and all bits to input ports. Port 7 as an input port. It also sets all bits of the output latch register P7 to 1. (1) P70 ( WAIT ) Port 70 is a general-purpose I/O port, and also used as an WAIT pin for external wait input. Reset Direction control (on bit basis) Internal data bus P7CR write S Output latch P70 ( WAIT ) P7 write S B Selector A P7 read WAIT (2) P71 to P77 Reset Direction control (on bit basis) Internal data bus P7CR write S Output latch P71 to P77 P7 write S B Selector A P7 read Figure 3.5.20 Port 7 93CS44-70 2004-02-10 TMP93CS44/S45 Port 7 Register 7 P7 (0013H) Bit symbol Read/Write After reset 1 1 1 1 P77 6 P76 5 P75 4 P74 R/W 3 P73 1 2 P72 1 1 P71 1 0 P70 1 Input mode Port 7 Control Register 7 P7CR (0015H) Prohibit readmodifywrite Bit symbol Read/Write After reset Function 0 0 0 0: Input 0 P77C 6 P76C 5 P75C 4 P74C W 3 P73C 0 1: Output 2 P72C 0 1 P71C 0 0 P70C 0 Port 7 I/O setting 0 Input 1 Output Note: P70/ WAIT pin does not have a register changing port/function. For example, when it is used as and input port, the input signal is inputted as WAIT input. When it is used as WAIT input pin, bit Figure 3.5.21 Register for Port 7 93CS44-71 2004-02-10 TMP93CS44/S45 3.6 Bus Width/Wait Controller and AM8/ AM16 Pin TMP93CS44/S45 have a built-in controller used to control wait ( WAIT pin) and data bus size (8 or 16 bits) for any of the three block address areas. And AM8/ AM16 pin selects external data bus width for TMP93CS45. 3.6.1 AM8/ AM16 pin (1) TMP93CS44 Set this pin to "H". After reset, the CPU accesses the internal ROM with 16-bit bus width. The bus width when the CPU accesses an external area is set by the bus width/wait control register (Described at 3.6.3) and the registers of Port 1. (The value 1 of this pin is ignored and the value set by register is active.) (2) TMP93CS45 1. With fixed external 16-bit data bus and external 16-bit data bus or 8-bit data bus is selectable Set this pin to "L". Port1, AD8 to AD15 and A8 to A15 pins are fixed to AD8 to AD15 functions. The values set in port 1 control register and port 1 function register are invalid. The external data bus width is set by the bus width/wait control register which is described in section 3.6.3. It is necessary to set the program memory to be accessed to 16-bit data bus after reset. 2. With fixed external 8-bit data bus Set this pin to "H". Port1, AD8 to AD15 and A8 to A15 pins are fixed to A8 to A15 functions. The values set in port 1 control register and port 1 function register are invalid. The values of bit4: 93CS44-72 2004-02-10 TMP93CS44/S45 3.6.2 Address/Data Bus Pins Port 0/AD0 to AD7, port 1/AD8 to AD15/A8 to A15 and port 2/A16 to A23/A0 to A7 function as address/data bus for connecting the external memories and so on. (1) Products (2) (3) (4) TMP93CS45F (Note 4) TMP93CS44F (Note 2), (Note 3) Max 8 (to 256 bytes) 16 0 VIH Number of Address Bus Max 24 (to 16 Mbytes) Max 24 (to 16 Mbytes) Max 16 (to 64 Kbytes) Pins Number of Data Bus Pins Number of Multiplexed Pins EA 8 8 VIL VIH AD0 to AD7 A8 to A15 A16 to A23 A23 to 8 AD7 to 0 A23 to 8 A7 to 0 D7 to 0 16 16 8 0 Mode Pins AM8/ AM16 Port 0 Port 1 Port 2 VIL AD0 to AD7 AD8 to AD15 A16 to A23 A23 to 16 VIH AD0 to AD7 A8 to A15 A0 to A7 A15 to 0 AD7 to 0 ALE A15 to 0 (Note 1) A7 to 0 D7 to 0 Port Function AD0 to AD7 AD8 to AD15 A0 to A7 A7 to 0 AD15 to 0 ALE A7 to 0 (Note 1) A15 to 0 D15 to 0 A23 to 16 A15 to 0 D15 to 0 AD15 to 0 Timing Chart ALE ALE RD RD RD RD Note 1: In case of (3) and (4), the data bus signals output the addresses since the signals are also used as the address bus. Writing "0" to bit CKOCR 93CS44-73 2004-02-10 TMP93CS44/S45 3.6.3 Bus Width/Wait Control Registers Figure 3.6.1 shows control registers. One block address areas are controlled by 1-byte bus width/wait control registers (WAITC0, WAITC1, WAITC2). (1) Data bus size select Bit4 ( These bits are initialized to 00 by reset. (3) Address area specification Control register bits 1 and 0 ( Setting bits to 01 enables setting for each block when 400000H to 7FFFFFH is accessed. Setting bits to 10 enables them 800000H to BFFFFFH is accessed. Setting bits to 11 enables them when C00000H to FFFFFFH is accessed. 93CS44-74 2004-02-10 TMP93CS44/S45 7 WAITC0 (0068H) Prohibit readmodifywrite Bit symbol Read/Write After reset Function 6 5 4 B0BUS 0 0: 16-bit bus 1: 8-bit bus B1BUS 0 0: 16-bit bus 1: 8-bit bus B2BUS 0 3 B0W1 0 00: 2 waits 01: 1 wait 10: (1 + N) waits 11: 0 waits B1W1 0 00: 2 waits 01: 1 wait 10: (1 + N) waits 11: 0 waits B2W1 0 2 B0W0 W 0 00: 01: 10: 11: 1 B0C1 0 0 B0C0 0 7F00H to 7FFFH From 400000H From 800000H From C00000H B1C0 0 WAITC1 (0069H) Prohibit readmodifywrite Bit symbol Read/Write After reset Function B1W0 W 0 B1C1 0 00: 01: 10: 11: 880H to 7FFFH From 400000H From 800000H From C00000H B2C0 0 WAITC2 (006AH) Prohibit readmodifywrite Bit symbol Read/Write After reset Function B2W0 W 0 B2C1 0 00: 01: 10: 11: 0: 16-bit 00: 2 waits bus 01: 1wait 1: 8-bit bus 10: (1 + N) waits 11: 0 waits From 8000H From 400000H From 800000H From C00000H Figure 3.6.1 Bus Width/Wait Control Registers Table 3.6.1 Dynamic Bus Sizing Operand Start Memory CPU Data CPU Address Address Data Size D15 to D8 D7 to D0 2n + 0 (Even number) 2n + 1 (Odd number) 16 bits 2n + 0 (Even number) 2n + 1 (Odd number) 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 32 bits 2n + 0 (Even number) 8 bits 2n + 0 2n + 0 2n + 1 2n + 1 2n + 0 2n + 1 2n + 0 2n + 1 2n + 2 2n + 1 2n + 2 2n + 0 2n + 1 2n + 2 2n + 3 16 bits 2n + 1 (Odd number) 8 bits 2n + 0 2n + 2 2n + 1 2n + 2 2n + 3 2n + 4 16 bits 2n + 1 2n + 2 2n + 4 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx b15 to b8 xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx b7 to b0 b7 to b0 b7 to b0 xxxxx b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 xxxxx b15 to b8 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 Operand Data Size 8 bits xxxxx: During a read, data input to the bus is ignored. At write, the bus is at high impedance and the write strobe signal remains non-active. 93CS44-75 2004-02-10 TMP93CS44/S45 3.6.4 Bus Width/Wait Control An image of the actual bus width/wait control is shown below. Out of the whole memory area, address areas that can be specified are divided into four parts. Addresses from 000000H to 3FFFFFH are divided differently: 7F00H to 7FFFH is specified for WAITC0; 880H to 7FFFH, for WAITC1; and 8000H to 3FFFFFH, for WAITC2. The reason is that a device other than ROM (e.g., RAM or I/O) might be connected externally. 7F00H to 7FFFH (256 bytes) for WAITC0 are mapped mainly for possible expansions to external I/O. 880H to 7FFFH (approx. 31 Kbytes) for WAITC1 are mapped there mainly for possible extensions to external RAM. 8000H to 3FFFFFH (approx. 4 Mbytes) for WAITC2 are mapped mainly for possible extensions to external ROM. With the TMP93CS45, which does not have a built-in ROM, the program is externally read at address FF0000H in this setting (16-bit bus, 2 waits). With the TMP93CS44 which has a built-in ROM, addresses from FF0000H to FFFFFFH are used as the internal ROM area; WAITC2 is disabled in this area. After reset, the CPU reads the program from the built-in ROM in 16-bit bus, 0 WAIT mode. WAITC0 000000H 7F00H 8000H 400000H Note 1: Access priority is highest for built-in I/O, then built-in memory, and lowest for the bus width/wait controller. Note 2: External areas other than WAITC0 to WAITC2 are accessed in 0 WAIT mode. In the TMP93CS45, when the AM8/ AM16 pin is set to "L", the data bus width is fixed to 16-bit. When the AM8/ AM16 pin is set to "H", it is fixed to 8 bits. In the TMP93CS44, the data bus width is always fixed to 16 bits. When using the bus width/wait controller, do not specify the same address area more than once. (However, when addresses 7F00H to 7FFFH for WAITC0 and 880H to 7FFFH for WAITC1 are specified, in other words, specifications overlap, only the WAITC0 setting is active.) 93CS44-76 2004-02-10 TMP93CS44/S45 3.6.5 Example of Usage (1) Example of usage-1 Figure 3.6.2 is an example in which an external memory is connected to the TMP93CS45. In this example, a ROM is connected using 16-bit bus; a RAM is connected using 8-bit bus. Decoder IOCS RAMCS ROMCS 74HC573 D TMP93CS45 Upper Address D ALE AD8 to AD15 AD0 to AD7 LE LE Q Address bus CS CS CS CS Q OE Upper byte ROM OE Lower byte ROM 8-bit bus RAM OE WE 8-bit bus I/O OE WE EA AM8/ AM16 RD WR Figure 3.6.2 Example of External Memory Connection (ROM = 16 bits, RAM and I/O = 8 bits) WAITC0 WAITC1 WAITC2 LD LD LD X: Don't care EQU EQU EQU (WAITC0), (WAITC1), (WAITC2), 68H 69H 6AH XXX10000B XXX11100B XXX00111B ; WAITC0 = 8 bits, 2 waits, 7F00H to 7FFFH. ; WAITC1 = 8 bits, 0 waits, 880H to 7EFFH. ; WAITC2 = 16 bits, 1 wait, C00000H to FFFFFFH. 93CS44-77 2004-02-10 TMP93CS44/S45 (1) Example of usage-2 Figure 3.6.3 is an example in which an external memory is connected to the TMP93CS45. In this example, a ROM, RAM, and I/O are connected using 8-bit bus. Decoder IOCS RAMCS ROMCS Address bus TMP93CS45 Upper Address ALE A8 to A15 AD0 to AD7 74HC573 CS CS CS D LE Q OE 8-bit bus ROM 8-bit bus RAM OE WE 8-bit bus I/O OE WE EA AM8/ AM16 RD WR Figure 3.6.3 Example of External Memory Connection (ROM, RAM and I/O = 8 bits) WAITC0 WAITC1 WAITC2 LD LD LD EQU EQU EQU (WAITC0), (WAITC1), (WAITC2), 68H 69H 6AH XXX10000B XXX11100B XXX00111B ; WAITC0 = 8 bits, 2 waits, 7F00H to 7FFFH ; WAITC1 = 8 bits, 0 waits, 880H to 7EFFH ; WAITC2 = 8 bits, 1 wait, C00000H to FFFFFFH X: Don't care 93CS44-78 2004-02-10 TMP93CS44/S45 (3) Example of usage-3 Figure 3.6.4 is an example in which an external memory is connected to the TMP93CS44. In this example, ROM 128 Kbytes are connected using 16-bit bus, and RAM 256 Kbytes are connected using 16-bit bus. Decoder ROMCS RAMCS TMP93CS44 Upper address Latch x 16 AD8 to AD15 D AD0 to AD7 LE Q Address bus ROM (128 Kbytes x 16) D8 to D15 D0 to D7 OE CS ALE RAM (128 Kbytes x 8) I/O1 to I/O8 RD HWR OE R/ W CS Upper byte WR RAM (128 Kbytes x 8) I/O1 to I/O8 OE R/ W CS AM8/ AM16 EA Lower byte Figure 3.6.4 Example of External Memory Connection (ROM and RAM = 16 bits) The TMP93CS44 has built-in ROM and RAM. When ROM and RAM have insufficient capacity, it is possible to connect an external memory as the example of the external memory connection. In this example, the memory configuration is as follows. Memory ROM SRAM Internal Internal Memory Size 64 Kbytes 2 Kbytes Address FF0000H to FFFFFFH 400000H to 41FFFFH 000080H to 00087FH 800000H to 83FFFFH Data Bus 16 bits 16 bits 16 bits 16 bits External 128 Kbytes External 256 Kbytes 93CS44-79 2004-02-10 TMP93CS44/S45 3.7 8-Bit Timers TMP93CS44/S45 contains four 8-bit timers (Timer 0, 1, 2, 3), each of which can be operated independently. The cascade connection allows these timers to be used as 16-bit timer. The following four operating modes are provided for the 8-bit timers. * * * * 8-bit interval timer mode (4 timers) 16-bit interval timer mode (2 timers) 8-bit programmable square wave pulse generation (PPG: Variable duty with variable cycle) output mode (1 timer) 8-bit pulse width modulation (PWM: Variable duty with constant cycle) output mode (1 timer) Figure 3.7.1 shows the block diagram of 8-bit timer (Timer 0, 1), and Figure 3.7.2 shows the block diagram of 8-bit timer (Timer 2, 3). Each interval timer consists of an 8-bit up counter, 8-bit comparator, and 8-bit timer register. Besides, timer flip-flops (TFF1, TFF3), are provided for pair of timer 0/1 and 2/3. Among the input clock sources for the interval timers, the internal clocks of T1, T4, T16, and T256 are obtained from the 9-bit prescaler shown in Figure 3.7.3. The operation modes and timer flip-flops of the 8-bit timer are controlled by five control registers T10MOD, T32MOD, TFFCR, TRUN and TRDC. 93CS44-80 2004-02-10 TRUN Timer F/F control RUN Clear RUN Clear TFFCR, T10MOD TFF1 (Timer 4, 5) Selector 2n - 1 over flow Selector T1 T16 T256 TI0 pin (External input) T1 T4 T16 8-bit up counter (UC0) 8-bit up counter (UC1) T10MOD Figure 3.7.1 Block Diagram of 8-Bit Timers (Timer 0 and 1) 93CS44-81 8-bit comparator (CP0) Match detect INTT0 8-bit timer register TREG0 Internal data bus 8-bit comparator (CP1) Match detect Selector T10MOD 8-bit timer register TREG1 INTT1 TMP93CS44/S45 2004-02-10 TRUN Timer F/F control RUN Clear RUN Clear TFFCR, T32MOD TFF3 TO3 (Shared pin with P41) T1 T4 T16 Selector 2n - 1 over flow Selector T1 T16 T256 8-bit up counter (UC2) 8-bit up counter (UC3) T32MOD Figure 3.7.2 Block Diagram of 8-Bit Timers (Timer 2 and 3) 93CS44-82 Match detect 8-bit comparator (CP2) INTT2 TO2TRG (to serial channels) Selector Register buffer TRDC 8-bit comparator (CP3) Match detect Selector T32MOD PPGTRG PWMTRG TREG-WR 8-bit timer register TREG3 INTT3 TMP93CS44/S45 2004-02-10 TMP93CS44/S45 1. Prescaler There are 9-bit prescaler and prescaler clock selection registers to generate input clock for 8-bit timer 0, 1, 2, 3, 16-bit timer 4, 5 and serial interface 0, 1. Figure 3.7.3 shows the block diagram. Table 3.7.1 shows prescaler clock resolution into 8, 16-bit timer. /2 fFPH to CPU System clock (fSYS) 9-bit prescaler 2 4 8 16 32 64 128 256 512 Selector /4 T1 T4 T16 T256 T1 T4 T16 1 T0 T2 T8 T32 to 8-bit timer 0, 1, 2, 3 XT1 fs TRUN Selector SYSCR0 to 16-bit timer 4, 5 to serial interface 0, 1 fc fc/2 fc/4 fc/8 fc/16 X1 /2 /4 /8 /16 SYSCR1 Figure 3.7.3 The Block Diagram of Prescaler Table 3.7.1 Prescaler Clock Resolution to 8- and 16-Bit Timer at fc = 20 MHz, fs = 32.768 kHz Select System Select Prescaler Clock Clock 1 (fs) Gear Value XXX 000 (fc) 001 (fc/2) 010 (fc/4) 011 (fc/8) 100 (fc/16) 3 Prescaler Clock Resolution T1 5 T4 7 T16 fs/2 (3.9 ms) fc/27 (6.4 s) fc/2 (12.8 s) 8 9 11 T256 fs/2 (62.5 ms) fc/211 (102.4 s) fc/212 (204.8 s) fc/213 (409.6 s) fc/214(819.2 s) fs/2 (244 s) fs/2 (977 s) fc/23 (0.4 s) fc/2 (0.8 s) 4 5 6 7 fc/25 (1.6 s) fc/2 (3.2 s) 6 7 8 9 0 (fc) 00 (fFPH) fc/2 (1.6 s) fc/2 (3.2 s) fc/2 (6.4 s) fc/2 (6.4 s) fc/2 (25.6 s) 10 11 fc/2 (12.8 s) fc/2 (51.2 s) fc/2 (25.6 s) fc/2 (102.4 s) fc/215 (1.6384 ms) fs/27 (3.9 ms) fs/211 (62.5 ms) XXX XXX 01 (Low-frequency clock) 10 (Note) (fc/16 clock) XXX: Don't care XXX XXX fs/23 (244 s) fs/25 (977 s) fs/27 (6.4 s) fc/29 (25.6 s) fc/211 (102.4 s) fc/215 (1.6384 ms) Note: The fc/16 clock as a prescaler clock can not be used when the fs is used as a system clock. 93CS44-83 2004-02-10 TMP93CS44/S45 The clock selected among fFPH clock, fc/16 clock, and fs clock is divided by 4 and input to this prescaler. This is selected by prescaler clock selection register SYSCR0 93CS44-84 2004-02-10 TMP93CS44/S45 3. Timer register This is an 8-bit register for setting an interval time. When the set value of timer registers TREG0, TREG1, TREG2, TREG3, matches the value of up counter, the comparator match detect signal becomes active. If the set value is 00H, this signal becomes active when the up counter overflows. Timer registers TREG2 are double buffer structure, each of which makes a pair with register buffer. The timer flip-flop controll register TRDC Up counter Comparator (CP2) Timer register 2 (TREG2) Matching detection of PPG cycle 2n - 1 overflow of PWM Selector TREG2WR Shift trigger Register buffer 2 Write Internal data bus TRDC Figure 3.7.4 Configuration of Timer Register 2 Note: Timer register and the register buffer are allocated to the same memory address. When The memory address of each timer register is as follows. TREG0: 000022H TREG1: 000023H TREG2: 000026H TREG3: 000027H All the registers are write only and cannot be read. 93CS44-85 2004-02-10 TMP93CS44/S45 4. Comparator A comparator compares the value in the up counter with the values to which the timer register is set. When they match, the up counter is cleared to zero and an interrupt signal (INTT0, INTT1, INTT2, INTT3) is generated. If the timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. 5. Timer flip-flop (Timer F/F: TFF1, TFF3) The timer flip-flop is a flip-flop inverted by the match detect signal (8-bit comparator output) of each interval timer. Inverting is disabled or enabled by the timer flip-flop control register TFFCR 93CS44-86 2004-02-10 TMP93CS44/S45 Timer Operation Control Register 7 TRUN (0020H) Bit symbol Read/Write After reset Function PRRUN R/W 0 0 6 5 T5RUN 4 T4RUN 3 T3RUN R/W 2 T2RUN 1 T1RUN 0 0 T0RUN 0 0 0 0 Prescaler and timer run/stop control 0: Stop and clear 1: Run (Count up) Count operation 0 Stop and clear 1 Count PRRUN: Operation of prescaler T5RUN : Operation of 16-bit timer (Timer 5) T4RUN : Operation of 16-bit timer (Timer 4) T3RUN : Operation of 8-bit timer (Timer 3) T2RUN : Operation of 8-bit timer (Timer 2) T1RUN : Operation of 8-bit timer (Timer 1) T0RUN : Operation of 8-bit timer (Timer 0) Note: TRUN System Clock Control Register 7 SYSCR0 (006EH) Bit symbol Read/Write After reset Function 1 0 1 0 Low-frequency oscillator (fs) after released STOP mode 0: Stop 1: Oscillation High-frequency Low-frequency High-frequency oscillator (fc) oscillator (fs) oscillator (fc) after released 0: Stop 0: Stop STOP mode 1: Oscillation 1: Oscillation 0: Stop 1: Oscillation 6 XTEN 5 RXEN 4 RXTEN R/W 3 RSYSCK 0 2 WUEF 0 1 PRCK1 0 0 PRCK0 0 XEN Select clock Warm-up after released timer (Write) STOP mode 0: Don't care 0: fc 1: Start timer 1: fs (Read) 0: End warm up 1: Not end warm up Select prescaler clock 00: fFPH 01: fs 10: fc/16 11: (Reserved) Select prescaler input clock 00 fFPH 01 10 11 fs fc/16 (Reserved) Figure 3.7.5 8-Bit Timer Related Registers (1/5) 93CS44-87 2004-02-10 TMP93CS44/S45 Timer 0, 1 Mode Control Register 7 T10MOD (0024H) Bit symbol Read/Write After reset Function 0 Operation mode 00: 8-bit timer 01: 16-bit timer 10: - 11: - 6 T10M0 R/W 0 5 4 3 T1CLK1 0 2 T1CLK0 R/W 0 1 T0CLK1 0 0 T0CLK0 0 T10M1 Source clock of timer 1 00: TO0TRG 01: T1 10: T16 11: T256 Source clock of timer 0 00: TI0 01: T1 10: T4 11: T16 Input clock of timer 0 00 External Input (TI0) 01 10 11 T1 (Prescaler) T4 (Prescaler) T16 (Prescaler) Input clock of timer 1 T10MOD 00 01 10 11 Comparator output Overflow output of timer 0 of timer 0 Internal clock T1 Internal clock T16 Internal clock T256 (16-bit timer mode) Set the operation mode of timer 0 and 1. 00 Two 8-bit timers (Timer 0 and timer 1) 01 16-bit timer 10 - 11 - Figure 3.7.6 8-Bit Timer Related Register (2/5) 93CS44-88 2004-02-10 TMP93CS44/S45 Timer 2 and Timer 3 Mode Control Register 7 T32MOD (0028H) Bit symbol Read/Write After reset Function 0 Operation mode 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM 6 T32M0 0 5 PWM21 0 PWM cycle 00: Don't care 01: 26 - 1 10: 27 - 1 11: 28 - 1 4 PWM20 R/W 0 3 T3CLK1 0 2 T3CLK0 0 1 T2CLK1 0 0 T2CLK0 0 T32M1 Source clock of timer 3 00: TO2TRG 01: T1 10: T16 11: T256 Source clock of timer 2 00: - 01: T1 10: T4 11: T16 Input clock of timer 2 00 Don't set 01 T1 (Prescaler) 10 T4 (Prescaler) 11 T16 (Prescaler) Input clock of timer 3 T32MOD 00 01 10 11 Comparator output Overflow output of timer 2 of timer 2 Internal clock T1 Internal clock T16 Internal clock T256 (16-bit timer mode) Select PWM cycle 00 Don't care 01 (26 - 1) x Input clock frequency of timer 2 10 (27 - 1) x Input clock frequency of timer 2 11 (28 - 1) x Input clock frequency of timer 2 Set the operation mode of timer 2 and 3. 00 Two 8-bit timers (Timer 0 and timer 1) 01 16-bit timer 10 8-bit PPG output 11 8-bit PWM output (Timer 2) 8-bit timer (Timer 3) Figure 3.7.7 8-Bit Timer Related Register (3/5) 93CS44-89 2004-02-10 TMP93CS44/S45 Timer Flip-Flop Control Register 7 TFFCR (0025H) Bit symbol Read/Write After reset Function 1 00: Invert TFF3 01: Set TFF3 10: Clear TFF3 11: Don't care 6 TFF3C0 W 1 5 TFF3IE R/W 0 TFF3 inversion trigger 0: Disable 1: Enable 4 TFF3IS 0 TFF3 inversion source 0: Timer 2 1: Timer 3 00: 01: 10: 11: 3 TFF1C1 W 1 Invert TFF1 Set TFF1 Clear TFF1 Don't care 2 TFF1C0 1 1 TFF1IE R/W 0 TFF1 inversion trigger 0: Disable 1: Enable 0 TFF1IS 0 TFF1 inversion source 0: Timer 0 1: Timer 1 TFF3C1 Select inverse signal of timer F/F3 ("Don't care" except in 8-bit timer mode) 0 Inversion by timer 2 1 Inversion by timer 3 Select inverse signal of timer F/F1 ("Don't care" except in 8-bit timer mode) 0 Inversion by timer 0 1 Inversion by timer 1 Inversion of timer F/F3 (TFF3) 0 Disable invert 1 Enable invert Inversion of timer F/F1 (TFF1) 0 Disable invert 1 Enable invert Control of timer F/F3 (TFF3) Invert the value of TFF3 00 (Software inversion) 01 Set TFF3 to "1" 10 Clear TFF3 to "0" 11 Don't care (Note) Control of timer F/F1 (TFF1) Invert the value of TFF1 00 (Software inversion) 01 Set TFF1 to "1". 10 Clear TFF1 to "0". 11 Don't care (Note) Note: TFFCR Figure 3.7.8 8-Bit Timer Related Register (4/5) 93CS44-90 2004-02-10 TMP93CS44/S45 Timer Register Double Buffer Control Register 7 TRDC (0029H) Bit symbol Read/Write After reset Function 0 0: Double buffer disable 1: Double buffer enable 6 5 4 3 2 1 TR2DE R/W 0 - 0 Always write "0". Operation of timer register 2 double butter 0 Disable 1 Enable Figure 3.7.9 8-Bit Timer Related Register (5/5) (1) 8-bit timer mode Four interval timers 0, 1, 2, 3 can be used independently as 8-bit interval timer. 1. Generating interrupts in a fixed cycle (in case of timer 1) To generate timer 1 interrupt at constant intervals using timer 1 (INTT1), first stop timer 1 then set the operation mode, input clock, and a cycle to T10MOD and TREG1 register, respectively. Then, enable interrupt INTT1 and start the counting of timer 1. Example: To generate timer 1 interrupt every 1 second at fs = 32 kHz, set each register in the following manner. * Clock condition System clock: Low frequency (fs) Prescaler clock: Low frequency (fs) TRUN T10MOD TREG1 INTET10 TRUN MSB 76543210 - X - - - - 0 - 0 0 X X 1 0 - - 1 1 1 1 1 0 1 X - 1 1 - 1 - - 0 - - 1 - 1 0 - ( LSB Stop timer 1, and clear it to "0". Set the 8-bit timer mode, and select T16 (4 ms at fs = 32 kHz) as the input clock. Set the timer register 1 s / T16 = 250 = FAH Enable INTT1, and set it to Level 5. Start timer 1 counting. X: Don't care, (: No change Use the Table 3.7.1 for selecting the input clock. Note: The input clock of timer 0 and timer 1 are different from as follows. Timer 0: TI0 input, (T1, (T4, (T16. Timer 1: Match output of timer 0, (T1, (T16, (T256. 93CS44-91 2004-02-10 TMP93CS44/S45 2. Generating a 50% duty square wave pulse The timer flip-flop is included in timer 1 and 3. The timer flip-flop (TFF3) is inverted at constant intervals, and its status is output to timer output pin (TO3). The output pin of TFF1 does not exist. Example: To output a 2.4 (s square wave pulse from TO3 pin at fc ( 20 MHz, set each register in the following procedures. Either timer 2 or timer 3 may be used, but this example uses timer 3. System clock: High frequency (fs) Clock gear: 1 (fc) Prescaler clock: fFPH * Clock condition TRUN T32MOD TREG3 TFFCR P4CR P4FC TRUN 76543210 - X - - 0 - - - 0 0 X X 0 1 - - 0 1 0 0 0 1 0 1 0 - 0 - 1 - 1 - Stop timer 3, and clear it to "0". Set the 8-bit timer mode, and select T1 (0.4 s at fc = 20 MHz) as the input clock. Set the timer register at 2.4 s / T1 / 2 = 3. Set TFF3 to "0", and set to invert by the match detect signal from timer 3. Select P41 as TO3 pin. Start timer 3 counting. - - - - - - 1 - - X X - X X 1 X - X - - 1 - - - X: Don't care, -: No change T1 TRUN TFF3 TO3 1.2 s at fc = 20 MHz Figure 3.7.10 Square Wave (50% duty) Output Timing Chart 93CS44-92 2004-02-10 TMP93CS44/S45 3. Making timer 1 count up by match signal from timer 0 comparator (Same function is achieved by using timer 3 and timer 2) Set the 8-bit timer mode, and set the comparator output of timer 0 as the input clock to timer 1. Comparator output (Timer 0 match) Timer 0 up counter (when TREG0 = 5) Timer 1 up counter (when TREG1 = 2) Timer 1 match output 1 2 3 1 4 5 1 2 3 2 4 5 1 2 1 3 Figure 3.7.11 Timer 1 Count up by Timer 0 (2) 16-bit timer mode A 16-bit interval timer is configured by using the pair of timer 0 and timer 1 or timer 2 and timer 3. To make a 16-bit interval timer by cascade connecting timer 0 and timer 1, set timer 0/1 mode register T10MOD Setting example: To generate an interrupt INTT3 every 0.4 seconds at fc = 20 MHz, set the following values for timer registers TREG2 and TREG3. System clock: High frequency (fs) Clock gear: 1 (fc) Prescaler clock: fFPH * Clock condition When counting with input clock of T16 (6.4 s at 20 MHz) 0.4 s / 6.4 s = 62500 = F424H Therefore, set TREG3 = F4H and TREG2 = 24H, respectively. 93CS44-93 2004-02-10 TMP93CS44/S45 The comparator match signal is output from timer 2 each time the up counter UC2 matches TREG2, where the up counter UC2 is not be cleared. With the timer 3 comparator, the match detect signal is output at each comparator timing when up counter UC3 and TREG3 values match. When the match detect signal is output simultaneously from both comparators of timer 2 and timer 3, the up counters UC2 and UC3 are cleared to 0, and the interrupt INTT3 is generated. If inversion is enabled, the value of the timer flip-flop TFF3 is inverted. Example: When TREG3 = 04H and TREG2 = 80H Value of up counter 0000H (UC3, UC2) Timer 2 comparator match detect signal Interrupt INTT3 Timer output TO3 Inversion 0080H 0180H 0280H 0380H 0480H Figure 3.7.12 Timer Output by 16-Bit Timer Mode (3) 8-bit PPG (Programmable pulse generation) output mode Square wave pulse can be generated at any frequency and duty by timer 2. The output pulse may be either low active or high active. In this mode, timer 3 cannot be used. Timer 2 outputs pulse to TO3 pin (Also used as P41). tH t tL TREG2 and UC2 match (Interrupt INTT2) TREG3 and UC2 match (Interrupt INTT3) TO3 TREG2 TREG3 Figure 3.7.13 8-Bit PPG Output Waveforms 93CS44-94 2004-02-10 TMP93CS44/S45 In this mode, a programmable square wave is generated by inverting timer output each time the 8-bit up counter (UC2) matches the timer registers TREG2 and TREG3. However, it is required that the set value of TREG2 is smaller than that of TREG3. Though the up counter (UC3) of timer 3 is not used in this mode, UC3 should be set for counting by setting TRUN TRUN Selector TFF3 TREG2 Selector TREG2-WR TRDC Internal data bus Figure 3.7.14 Block Diagram of 8-Bit PPG Output Mode When the double buffer of TREG2 is enabled in this mode, the value of register buffer will be shifted in TREG2 each time TREG3 matches UC2. Use of the double buffer makes easy the handling of low duty waves (when duty is varied). Match with TREG2 and up counter (Up counter = Q1) Match with TREG 3 Shift from register buffer TREG2 (Value to be compared) Register buffer Q1 Q2 Q2 Q3 TREG 2 (Register buffer) write (Up counter = Q2) Figure 3.7.15 Operation of Register Buffer 93CS44-95 2004-02-10 TMP93CS44/S45 Example: Generating 1/4 duty 62.5 kHz pulse (at fc = 20 MHz) 16 s * Clock condition System clock: High frequency (fs) Clock gear: 1 (fc) Prescaler clock: fFPH Calculate the value to be set for timer register. To obtain the frequency 62.5 kHz, the pulse cycle t should be: t = 1/62.5 kHz = 16 s. Given T1 = 0.4 s (at 20 MHz), 16 s / 0.4 s = 40 Consequently, to set the timer register 3 (TREG3) to TREG3 = 40 = 28H and then duty to 1/4, t x 1/4 = 16 s x 1/4 = 4 s 4 s / 0.4 s = 10 Therefore, set timer register 2 (TREG2) to TREG2 = 10 = 0AH. 76 -X 10 00 00 01 5 - X 0 1 1 4 - X 0 0 X 3 0 X 1 1 - 2 0 X 0 0 - 1 - 0 1 0 - 0 - 1 0 0 - TRUN T32MOD TREG2 TREG3 TFFCR Stop timer 2, 3 and clear it to "0". Set the 8-bit PPG mode, and select T1 as input clock. Write "0AH". Write "28H". Sets TFF3 and enable the inversion and double buffer enable. Writing "10" provides negative logic pulse. Set P41 as the TO3 pin. Start timer 2 and timer 3 counting. P4CR P4FC TRUN - - - - - - 1 - - X X - X X 1 X 1 X - - 1 1 - - X: Don't care, -: No change 93CS44-96 2004-02-10 TMP93CS44/S45 (4) 8-bit PWM Output mode This mode is valid only for timer 2. In this mode, maximum 8-bit resolution of PWM pulse can be output. PWM pulse is output to TO3 pin (also used as P41) when using timer 2. Timer 3 can also be used as 8-bit timer. Timer output is inverted when up counter (UC2) matches the set value of timer register TREG2 or when 2n - 1 (n = 6, 7 or 8; specified by T32MOD |